March 2015 Archives by thread

• Messages sorted by: [ subject ] [ author ] [ date ]
• More info on this list...

Starting: Wed Mar 4 21:30:26 UTC 2015
Ending: Tue Mar 31 20:38:29 UTC 2015
Messages: 337

• [Cryptech-Commits] [user/paul/core] branch platform created (now 35d98f4)   git at cryptech.is
  • [Cryptech-Commits] [user/paul/core] 01/01: Group cores by function (hash, cipher, rng, comm, platform).   git at cryptech.is
• [Cryptech-Commits] [core/sha3] branch master created (now 771fb75)   git at cryptech.is
  • [Cryptech-Commits] [core/sha3] 01/01: Adding initial version of license and readme files.   git at cryptech.is
• [Cryptech-Commits] [core/sha3] branch master updated (771fb75 -> cfbd328)   git at cryptech.is
  • [Cryptech-Commits] [core/sha3] 01/01: Adding initial version of sha3 core by Bernd Paysan.   git at cryptech.is
• [Cryptech-Commits] [core/sha256] branch master updated (bbfa764 -> 4b24edf)   git at cryptech.is
  • [Cryptech-Commits] [core/sha256] 01/01: Removed the wishbone wrapper we don't use.   git at cryptech.is
• [Cryptech-Commits] [core/sha3] branch master updated (cfbd328 -> b540219)   git at cryptech.is
  • [Cryptech-Commits] [core/sha3] 01/01: Adding initial version of tb for sha3 core.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (a98f5c8 -> b56da05)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: Adding FPGA resource tracker and estimates document.   git at cryptech.is
• [Cryptech-Commits] [core/modexp] branch master created (now fec98c9)   git at cryptech.is
  • [Cryptech-Commits] [core/modexp] 01/01: Adding license and initial readme for the modexp core. Provides at least a high level intro to the core and current status.   git at cryptech.is
• [Cryptech-Commits] [core/modexp] branch master updated (fec98c9 -> ed86ff4)   git at cryptech.is
  • [Cryptech-Commits] [core/modexp] 01/01: Adding c model for the modexp core.   git at cryptech.is
• [Cryptech-Commits] [core/modexp] branch master updated (ed86ff4 -> dfe1b77)   git at cryptech.is
  • [Cryptech-Commits] [core/modexp] 01/01: Adding java rsa functional model.   git at cryptech.is
• [Cryptech-Commits] [test/novena_base] branch trng created (now 97f0335)   git at cryptech.is
  • [Cryptech-Commits] [test/novena_base] 01/01: (1) First attempt at connecting the rng core into the novena. (2) Fixed minor copy crimes. (3) autmagically removed trailing whitespace.   git at cryptech.is
• [Cryptech-Commits] [test/novena_base] branch trng updated (97f0335 -> 0bdca3b)   git at cryptech.is
  • [Cryptech-Commits] [test/novena_base] 01/01: Fixed names for core selector to follow the form of the selectors for rng and ciphers. Fixed copy crimes. Disabled hash cores for the time being since we want to debug the rng.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (b56da05 -> c122957)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/02: overview of HSM internal keys and how they relate   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 02/02: some early sketches on application aware signing   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (c122957 -> 4e6e362)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: add alpha board overview based on design from Fredrik and Joachim   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (4e6e362 -> 2509648)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/02: cleanup   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 02/02: export to PDF   git at cryptech.is
• [Cryptech-Commits] [user/paul/core] branch platform updated (35d98f4 -> 0d9381c)   git at cryptech.is
  • [Cryptech-Commits] [user/paul/core] 01/01: Move novena_clkmgr to platform/novena/common, so that i2c can use it.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (2509648 -> 2532839)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: add CKM_ECDSA_SHA256   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (2532839 -> 7af8d86)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: minor updates   git at cryptech.is
• [Cryptech-Commits] [staging/core/cipher/aes] branch master created (now b07918a)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 01/08: Adding readme for the aes core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 02/08: Adding license file too.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 03/08: Adding RTL source files for the AES core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 04/08: Adding testbenchs.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 05/08: Adding Python models for AES as well as key expansion and rcon.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 06/08: Adding Makefile for building simulation targets.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 07/08: Removed obsolete target.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/aes] 08/08: Reworked the sbox and inverse sbox. Slighly smaller design and much shorter source files.   git at cryptech.is
• [Cryptech-Commits] [staging/core/cipher/chacha] branch master created (now 5786690)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 01/07: Adding text files for license and general info.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 02/07: Adding RTL code for the ChaCha stream cipher.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 03/07: Adding testbenches for core and top.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 04/07: Adding a Python functional model of the ChaCha stream cipher.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 05/07: Adding Makefile for building and running chacha simulations.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 06/07: Update of ChaCha with fixes found during synthesis.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/cipher/chacha] 07/07: Fixes to nits found using the verilator linter.   git at cryptech.is
• [Cryptech-Commits] [staging/core/comm/coretest] branch master created (now 3859848)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 01/10: Adding source files for coretest.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 02/10: Adding makefile to buld and run coretest simulation.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 03/10: Adding license and readme file.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 04/10: Adding extra state to fix combinational loop.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 05/10: Disabling verbose mode.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 06/10: Adding ModelSim wave viewer setup for coretest.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 07/10: Update of coretest to new, reworked parser. This fixes problems with SOC and EOC in address or data.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 08/10: Update of testbench with monitor for test core access, new test cases etc.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 09/10: Fixed nits. Removed trailing whitespace.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/coretest] 10/10: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/comm/eim] branch master created (now 755bd6f)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/eim] 01/01: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/comm/i2c] branch master created (now ba1b8e7)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/i2c] 01/05: initial commit of I2C code for coretest   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/i2c] 02/05: fix i2c read buffer overrun   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/i2c] 03/05: correct size of I2C FSM state values   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/i2c] 04/05: i2c_device_addr as output   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/i2c] 05/05: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/comm/uart] branch master created (now fa9d69e)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 01/13: Adding license and readme files for the uart.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 02/13: Adding RTL files for the uart.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 03/13: Adding testbench for the uart.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 04/13: Adding Python program to test the uart.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 05/13: Adding makefile to build and run uart simulations.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 06/13: Adding size constraints to constant definitions to remove synthesis warnings.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 07/13: Changing from blocking to correct, non-blocking assignments in reg update.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 08/13: Adding support for setting bit rate, data- and stop bits.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 09/13: Update of core to use bitrate, data bits and stop bits supplied via ports.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 10/13: Update of core address size to 8 bits. Changed use of bit rate, data and stop bits from the top.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 11/13: Adding a note about the new ability to change bit rate as well as number of data- and stop bits.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 12/13: Changed to asynch reset.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/comm/uart] 13/13: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/hash/sha1] branch master created (now d76f15b)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 01/20: Adding Makefile for compiling and running simulations of the sha1 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 02/20: Adding license file.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 03/20: Adding README file in markdown format.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 04/20: Adding functional model in Python. Used to drive RTL development.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 05/20: Adding all rtl source files for the sha-1 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 06/20: Adding all testbenches.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 07/20: Updated W memory module with new sliding window version. Updated README with more info.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 08/20: Adding more info about the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 09/20: Adding info about the sha1 design.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 10/20: Updating interface. Addding self resetting control regs. Fixing missing input port declaration that caused errors during simulation in ModelSim.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 11/20: Added wait to allow the ready flag to be dropped with resettable flags. Fixed name of clock delay parameter.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 12/20: Removed redundant flag reset wires.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 13/20: Update of the Python model to support NIST dual block message test as well as a test case with a huge message.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 14/20: (1) Minor fixes of nits found by the verilator linter. (2) Removed trailing whitespace.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 15/20: Changed to asynch reset.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 16/20: Updated the README to hopefully make it more readable.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 17/20: Adding API table.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 18/20: Adding a separate digiest update state.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 19/20: There is an END to this, according to Paul.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha1] 20/20: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/hash/sha256] branch master created (now 4b63312)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 01/32: Adding license description for the sha256 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 02/32: Adding makefile for building and simulating the sha256 design.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 03/32: Adding K constant memory source file.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 04/32: Adding the W memory including scheduler and expansion functionality.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 05/32: Source for the main part of the sha256 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 06/32: Adding top level wrapper for the sha256. This wrapper provides a simple memory like interface.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 07/32: Adding a Wishbone wrapper for the SHA256 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 08/32: Adding a testbench for the w memory module.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 09/32: Adding a testbench for the SHA256 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 10/32: Adding a testbench for the SHA256 top level wrapper.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 11/32: Adding a testbench for the Wishbone wrapper.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 12/32: Adding a Python model for the SHA256 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 13/32: Adding a simple README file in markdown format that describes the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 14/32: Changed W-memory into sliding window. This also affected interface and integration in the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 15/32: Updated testbenches to the new sliding window W-mem.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 16/32: Updated status with info on the sliding window W-mem and the new implementation results.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 17/32: Moved wmem update logic to a separate process.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 18/32: Update or README with more info on status.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 19/32: Fixed compile problems due to copy crime.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 20/32: Updating README with info on the design.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 21/32: Adding more info about the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 22/32: Changed the python model to use a sliding window for W.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 23/32: Removed the positions of W no longer needed.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 24/32: (1) Updated interface to new std. (2) Added missing input designation in tasks. Now simumaltion with ModelSim works.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 25/32: Adding self resetting init and next flags. Updating TBs to not reset the flags. Fixing clock parameter naming.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 26/32: Removed redundant flag reset wires.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 27/32: Updating sha256 python model with NIST dual block test case and test case with huge message. Disabling verbose mode.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 28/32: Adding helper functions for printing digest. Adding testcase for message with 1000 blocks.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 29/32: Fixed nits found using verilator linter. Removed trailing whitespace.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 30/32: Changed to asynch reset.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 31/32: Removed the wishbone wrapper we don't use.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha256] 32/32: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/hash/sha3] branch master created (now b540219)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha3] 01/03: Adding initial version of license and readme files.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha3] 02/03: Adding initial version of sha3 core by Bernd Paysan.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha3] 03/03: Adding initial version of tb for sha3 core.   git at cryptech.is
• [Cryptech-Commits] [staging/core/hash/sha512] branch master created (now b2d92aa)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 01/09: Adding license and README file for the sha512 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 02/09: Adding Makefile for building sha512 simulation targets.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 03/09: Adding core and top level testbenches for sha512.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 04/09: Adding source RTL files for the sha512 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 05/09: Adding the Python functional model of the SHA-512 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 06/09: Changed to asynch reset.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 07/09: Fixes of nits in #8 found with the verilator linter.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 08/09: Adding work factor processing functionality.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/hash/sha512] 09/09: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/math/modexp] branch master created (now dfe1b77)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/math/modexp] 01/03: Adding license and initial readme for the modexp core. Provides at least a high level intro to the core and current status.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/math/modexp] 02/03: Adding c model for the modexp core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/math/modexp] 03/03: Adding java rsa functional model.   git at cryptech.is
• [Cryptech-Commits] [staging/core/platform/common] branch master created (now 63c5dae)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/common] 01/01: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/platform/novena] branch master created (now 283bfbe)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 01/08: initial commit of Novena code for coretest   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 02/08: hash_tester should read the correct number of response bytes   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 03/08: Add a generic file hashing utility, and some test files.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 04/08: fix status bits as values, not positions   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 05/08: do proper SHA* padding   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 06/08: i2c_device_addr as output   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 07/08: change synth/ to build/, add .gitignore   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/novena] 08/08: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/platform/terasic_c5g] branch master created (now 3c36fb8)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 01/20: Adding readme and license for the coretest_hashes subsystem.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 02/20: Adding RTL to build the coretest_hashes subsystem with SHA-1 and SHA-256 cores.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 03/20: Adding Makefile to build the coretest_hashes subsystem.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 04/20: Updating address for uart to 8 bits which should be the default.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 05/20: Adding test program that checks the SHA-1 and SHA-256 cores and do single block hashing.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 06/20: Adding bitstream file for coretest_hashes on the TerasIC C5G board.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 07/20: Adding project, assignment and clock setup files for Quartus and the TerasIC C5G board.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 08/20: Refactored code to allow additions of test cases. Adding dual block message test cases as specified by NIST. Adding code for running huge message test. This test case si disabled due to bugs in coretest.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 09/20: Update of prebuilt FPGA configuration with new coretest.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 10/20: Update of coretest_hashes to also include the sha512 core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 11/20: Adding prebuilt coretest_hashes that includes SHA-512.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 12/20: (1) Added functionality to do single block tests of all SHA-512/x modes. (2) Major cleanup of nits and magic constants. Moved all test cases to separate functions. Added support to enable/disable tests.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 13/20: Adding test case for dual block tests of SHA-512/x. All tests passed. Separated delays into comm vs processing. Updated comment in header to reflect SHA-512/x.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 14/20: Fixed error in (c). Drastically reduced processing delay. Adding missing expected digest for SHA-384.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 15/20: Added functionality to change baud rate. Decreased comm delay. Now test cases goes much faster.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 16/20: Adding new prebuilt FPGA with uart that supports change of bitrate.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 17/20: Enabling all test cases again.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 18/20: Fixed huge message test. We now run test of message with 100 blocks in SHA-256.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 19/20: Increased communication speed. Increased number of blocks in huge mesage test to 1000 blocks.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/platform/terasic_c5g] 20/20: Rearrange cores.   git at cryptech.is
• [Cryptech-Commits] [staging/core/rng/avalanche_entropy] branch master created (now e824aac)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 01/08: Adding a new core for avalanche noise based entropy.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 02/08: Adding a simple readme about the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 03/08: Moved the readme to correct place.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 04/08: Update efter synthesis. Adding a top level wrapper.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 05/08: Updated headers.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 06/08: Adding Makefile for compiling the avalanche entropy source.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 07/08: Refactor code to have the main entropy functionality in the core and api in the wrapper.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/avalanche_entropy] 08/08: Adding hard coded core name and version strings accessible through the core api.   git at cryptech.is
• [Cryptech-Commits] [staging/core/rng/rosc_entropy] branch master created (now a7b141c)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 01/11: Adding a new core for ring oscillator based entropy.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 02/11: Updates to fix bugs found during synthesis. Adding more debug outputs in API. Adding security error port for future internal health tests.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 03/11: Adding an enable signal port for any consumers to know that the provider is active.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 04/11: Fixed synthesis warnings.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 05/11: Adding very breaf readme.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 06/11: Update of rosc entropy after synthesis of the trng.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 07/11: Changed name of register to make it more obvious what it is.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 08/11: Added Xilinx specific constraint attribute to preserve the ring oscillators. Fixed name of rosc instances.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 09/11: Adding missing license file for the rosc_entropy core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 10/11: Added Bernd Paysan as author.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/rosc_entropy] 11/11: Added addresses and hard coded strings for name and version accessible from API. Updated API addresses.   git at cryptech.is
• [Cryptech-Commits] [staging/core/rng/trng] branch master created (now 7bb7bdf)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 01/30: Adding readme and license for the trng core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 02/30: Adding rtl and tb for the csprng part of the trng.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 03/30: Adding makefile.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 04/30: Adding compile and sim target for the mixer.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 05/30: Adding initial versions of rtl and tb for the mixer.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 06/30: Update after completion of rtl and debug of rtl using the updated testbench. Now it works.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 07/30: Adding fake modules for the three types of entropy sources to allow us to simulate with known values.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 08/30: Adding testbench for the complete trng.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 09/30: Adding first version of complete trng.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 10/30: Updated Makefile to build the complete trng simulation target.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 11/30: Debug fixes found during simulation. Now the trng generates data and provides an api.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 12/30: More debug fixes. We add one extra wait cycle to allow the mixer to detect that we want more seed.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 13/30: Fixed incorrect bit index.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 14/30: Adding initial version of wrapper for the avalance entropy core to be used during synthesis.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 15/30: Adding a minor readme to explain when to use the entropy wrappers.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 16/30: Adding implemenatation notes that explains the different models for simulation and synthesis of the entropy sources.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 17/30: Updates after synthesis of the complete trng.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 18/30: Update of fake entropy sources used in simulation.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 19/30: Removing old fake module for ring oscillator.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 20/30: Removing old fake entropy source.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 21/30: Updating source to the latest and greatest. In this version the entropy sources works and all modules have correct intterface.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 22/30: Adding debug port for mixer and csprng. In the csprng the debug_update will trigger fifo extraction and thus force random number generation.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 23/30: Updating trng to debugged version.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 24/30: Removing wrappers since they are not used.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 25/30: Updating testbenches to match new interfaces and use the api to read and write data.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 26/30: Adding Quartus project files to build trng for TerasIC DE0 Nano board. This also includes a prebuilt config file.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 27/30: (1) Reducing timepout for entropy sources. Updated interface for sha-512 to match new interface with work factor ports. We are not using the work factor here at the moment.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 28/30: Updates after linting.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 29/30: Reworked the csprng output fifo to really take advantage of the fact that the csprng delivers blocks of 512 bits. Removed trailing whitespaces and linted code.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/trng] 30/30: Updates of variable names to matched changed instance name and new fifo.   git at cryptech.is
• [Cryptech-Commits] [staging/core/rng/vndecorrelator] branch master created (now 49e388c)   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/vndecorrelator] 01/03: Adding license and README file that gives a brief description of the core.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/vndecorrelator] 02/03: Adding rtl source file and testench for the von Neumann decorrelator.   git at cryptech.is
  • [Cryptech-Commits] [staging/core/rng/vndecorrelator] 03/03: Adding Makefile for building the von Neumann simulation.   git at cryptech.is
• [Cryptech-Commits] [test/test_core] branch master created (now 240a517)   git at cryptech.is
  • [Cryptech-Commits] [test/test_core] 01/02: Adding license and readme for the test_core.   git at cryptech.is
  • [Cryptech-Commits] [test/test_core] 02/02: Adding RTL for the test_core.   git at cryptech.is
• [Cryptech-Commits] [test/coretest_test_core] branch master created (now 497c12c)   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 01/08: Adding license and readme file for the coretest_test_core subsystem.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 02/08: Adding sw to run tests on a FPGA device connected to the FPGA board via a serial port.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 03/08: Adding symbolic name and comment to highlight the serial port device.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 04/08: Adding the RTL that builds the subsystem.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 05/08: Adding testbench for the coretest_test_core subsystem.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 06/08: Adding Makefile for building and running simulations.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 07/08: Adding a prebuilt FPGA configuration file for the TerasIC C5G board.   git at cryptech.is
  • [Cryptech-Commits] [test/coretest_test_core] 08/08: Adding clock define.   git at cryptech.is
• [Cryptech-Commits] [test/novena_i2c_simple] branch master created (now 70b08c1)   git at cryptech.is
  • [Cryptech-Commits] [test/novena_i2c_simple] 01/04: Initial commit   git at cryptech.is
  • [Cryptech-Commits] [test/novena_i2c_simple] 02/04: do proper SHA* padding   git at cryptech.is
  • [Cryptech-Commits] [test/novena_i2c_simple] 03/04: i2c_device_addr as output   git at cryptech.is
  • [Cryptech-Commits] [test/novena_i2c_simple] 04/04: add .gitignore   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (7af8d86 -> 452c812)   git at cryptech.is
• [Cryptech-Commits] [doc/design] 01/01: Adding Alpha board drawing. This version fixes a few nits.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (452c812 -> 6a2f5a3)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: Update after feedback. Fixed labels on wires and repositioned USB-SPI trasnscievers.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (6a2f5a3 -> 9cc7045)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: Update after feedback. Added battery and crystal to to the RTC.   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (9cc7045 -> 7dbd08f)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: Added info about FPGA config memory.   git at cryptech.is
• [Cryptech-Commits] [user/sra/git-config-test] branch master created (now ee84bad)   git at cryptech.is
  • [Cryptech-Commits] [user/sra/git-config-test] 01/01: Content for git configuration test, nothing to see here.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (7bb7bdf -> 6278909)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: streamline(?) api_mux, register data for eim output   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (e824aac -> 371b7e3)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: register data for eim output   git at cryptech.is
• [Cryptech-Commits] [core/rng/rosc_entropy] branch master updated (a7b141c -> cbd0a69)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/rosc_entropy] 01/01: register data for eim output   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch master updated (63c5dae -> 989c112)   git at cryptech.is
  • [Cryptech-Commits] [core/platform/common] 01/01: integrate trng into core_selector framework   git at cryptech.is
• [Cryptech-Commits] [core/platform/novena] branch master updated (283bfbe -> 2b874d3)   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 01/01: integrate trng into core_selector framework   git at cryptech.is
• [Cryptech-Commits] [doc/design] branch master updated (7dbd08f -> 31f4b06)   git at cryptech.is
  • [Cryptech-Commits] [doc/design] 01/01: Update of Alpha board drawing to change host and management interfaces to UART with updated interface chips. Updated EIM interface to 16 bit address bus. Updated PSU primary rail info. Added symbols for CPU clock and reset blocks. Added info about Tamper MCU clocking.   git at cryptech.is
• [Cryptech-Commits] [core/rng/rosc_entropy] branch master updated (cbd0a69 -> b93eb8b)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/rosc_entropy] 01/01: Changed fromm hard coded oscillator adder width to localparam and updated operand sizes used. Changed to localparams for parameters since they don't need to be exposed outside the module. Updated the oscillator array instantiation to reflect what is done.   git at cryptech.is
• [Cryptech-Commits] [core/rng/rosc_entropy] branch master updated (b93eb8b -> 4e44653)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/rosc_entropy] 01/01: Adding a README for the rosc entropy source with a short description of what the core is, how it works and implementation status for different FPGAs.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (371b7e3 -> e606f92)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Adding missing license file.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (e606f92 -> 26bc2a2)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Cleanup: Combined the clocked processes into one. Changed name of the data read register to reflect that it is a hold register. Fixed missing port and removed the unneeded assignment.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (26bc2a2 -> 156ca94)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Updating the core README with info about what the core is, how it works and implememtation status.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (156ca94 -> b6e2b9c)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Adding a minor comment about tool used during testing.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (b6e2b9c -> c24da16)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Spelling errors and fix of core name in README.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (6278909 -> aa3ba0f)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Updated the Makefile to match the new CT repo structure.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (aa3ba0f -> b117149)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Cleanup: Merged separate clocked processes. Fixed incorrect bit widths. Changed to localparams. Changed api data read reg to real hold register.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (b117149 -> 87f0f8f)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Cleanup from linting. Changing to parameterized fifo pointers. Fixed bug in bit selection.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (87f0f8f -> 43a9547)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: More cleanup. Completed parameterization of fifo. Fixed incorrect size of control regs.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (43a9547 -> cf41753)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Changed to Verilog 2001 part select for word extraction.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (cf41753 -> 7c6b8ab)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Minor cleanup: Changed to localparam for internal parameters. Merged reg update processes to one. Changed name of api read data hold reg and added better update vector name for it.   git at cryptech.is
• [Cryptech-Commits] [core/rng/trng] branch master updated (7c6b8ab -> 36fe252)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/trng] 01/01: Minor cleanup: Morged clocked processes. Changed name of api read data hold register. Changed to localparam. Removed redundant code for reg updates.   git at cryptech.is
• [Cryptech-Commits] [core/rng/avalanche_entropy] branch master updated (c24da16 -> 4fcba84)   git at cryptech.is
  • [Cryptech-Commits] [core/rng/avalanche_entropy] 01/01: Minor cleanup. Changed to localparams.   git at cryptech.is
• [Cryptech-Commits] [core/comm/coretest] branch master updated (3859848 -> a9dd663)   git at cryptech.is
  • [Cryptech-Commits] [core/comm/coretest] 01/01: Revert previous commit - don't delay reads for the sake of EIM.   git at cryptech.is
• [Cryptech-Commits] [core/comm/eim] branch master updated (755bd6f -> a40c577)   git at cryptech.is
  • [Cryptech-Commits] [core/comm/eim] 01/01: Don't delay register reads in eim_regs.   git at cryptech.is
• [Cryptech-Commits] [core/comm/uart] branch master updated (fa9d69e -> 1522057)   git at cryptech.is
  • [Cryptech-Commits] [core/comm/uart] 01/02: Don't delay register reads in uart_regs.   git at cryptech.is
  • [Cryptech-Commits] [core/comm/uart] 02/02: Fix testbench to match new file organization.   git at cryptech.is
• [Cryptech-Commits] [core/hash/sha1] branch master updated (d76f15b -> febb275)   git at cryptech.is
  • [Cryptech-Commits] [core/hash/sha1] 01/01: Revert streamlined wrapper, and don't delay register reads.   git at cryptech.is
• [Cryptech-Commits] [core/hash/sha256] branch master updated (4b63312 -> ce56b11)   git at cryptech.is
  • [Cryptech-Commits] [core/hash/sha256] 01/02: Revert streamlined wrapper, and don't delay register reads.   git at cryptech.is
  • [Cryptech-Commits] [core/hash/sha256] 02/02: Remove wishbone testbench code, because we no longer have the verilog.   git at cryptech.is
• [Cryptech-Commits] [core/hash/sha512] branch master updated (b2d92aa -> 51ad57c)   git at cryptech.is
  • [Cryptech-Commits] [core/hash/sha512] 01/01: Revert streamlined wrapper, and don't delay register reads.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch master updated (989c112 -> 7549174)   git at cryptech.is
  • [Cryptech-Commits] [core/platform/common] 01/01: Conditionalize trng so it can be easily excluded.   git at cryptech.is
• [Cryptech-Commits] [core/platform/novena] branch master updated (2b874d3 -> 17d551b)   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 01/05: Move eim read delay to novena_eim.v.   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 02/05: Move novena_regs.v to common, fix to match other register read/write blocks.   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 03/05: Build i2c with rng cores.   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 04/05: Refactor common code into tc_[eim|i2c].[ch], add general-purpose hash utilities, add trng_tester_i2c.   git at cryptech.is
  • [Cryptech-Commits] [core/platform/novena] 05/05: Move novena_regs.v to common (fb35379)   git at cryptech.is

Last message date: Tue Mar 31 20:38:29 UTC 2015
Archived on: Tue Mar 31 20:38:31 UTC 2015

• Messages sorted by: [ subject ] [ author ] [ date ]
• More info on this list...