[Cryptech-Commits] [staging/core/platform/terasic_c5g] 10/20: Update of coretest_hashes to also include the sha512 core.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository staging/core/platform/terasic_c5g.

commit 9dd538460a090b9cc65bc4bd336445b157b75d7f
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Wed May 7 15:41:20 2014 +0200

    Update of coretest_hashes to also include the sha512 core.
---
 src/rtl/coretest_hashes.v | 45 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 44 insertions(+), 1 deletion(-)

diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v
index d3fda6a..34208c5 100644
--- a/src/rtl/coretest_hashes.v
+++ b/src/rtl/coretest_hashes.v
@@ -9,7 +9,7 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
 // All rights reserved.
 // 
 // Redistribution and use in source and binary forms, with or 
@@ -57,6 +57,7 @@ module coretest_hashes(
   parameter UART_ADDR_PREFIX   = 8'h00;
   parameter SHA1_ADDR_PREFIX   = 8'h10;
   parameter SHA256_ADDR_PREFIX = 8'h20;
+  parameter SHA512_ADDR_PREFIX = 8'h30;
   
   
   //----------------------------------------------------------------
@@ -103,6 +104,15 @@ module coretest_hashes(
   wire [31 : 0] sha256_read_data;
   wire          sha256_error;
   wire [7 : 0]  sha256_debug;
+
+  // sha512 connections.
+  reg           sha512_cs;
+  reg           sha512_we;
+  reg [7 : 0]   sha512_address;
+  reg [31 : 0]  sha512_write_data;
+  wire [31 : 0] sha512_read_data;
+  wire          sha512_error;
+  wire [7 : 0]  sha512_debug;
   
   
   //----------------------------------------------------------------
@@ -197,6 +207,23 @@ module coretest_hashes(
                );
 
   
+  sha512 sha512(
+                // Clock and reset.
+                .clk(clk),
+                .reset_n(reset_n),
+
+                // Control.
+                .cs(sha512_cs),
+                .we(sha512_we),
+
+                // Data ports.
+                .address(sha512_address),
+                .write_data(sha512_write_data),
+                .read_data(sha512_read_data),
+                .error(sha512_error)
+               );
+
+
   //----------------------------------------------------------------
   // address_mux
   //
@@ -224,6 +251,11 @@ module coretest_hashes(
       sha256_address     = 8'h00;
       sha256_write_data  = 32'h00000000;
 
+      sha512_cs          = 0;
+      sha512_we          = 0;
+      sha512_address     = 8'h00;
+      sha512_write_data  = 32'h00000000;
+
 
       case (coretest_address[15 : 8])
         UART_ADDR_PREFIX:
@@ -257,6 +289,17 @@ module coretest_hashes(
             coretest_read_data = sha256_read_data;
             coretest_error     = sha256_error;
           end
+
+
+        SHA512_ADDR_PREFIX:
+          begin
+            sha512_cs          = coretest_cs;
+            sha512_we          = coretest_we;
+            sha512_address     = coretest_address[7 : 0];
+            sha512_write_data  = coretest_write_data;
+            coretest_read_data = sha512_read_data;
+            coretest_error     = sha512_error;
+          end
         
         
         default: