[Cryptech-Commits] [staging/core/platform/terasic_c5g] 16/20: Adding new prebuilt FPGA with uart that supports change of bitrate.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository staging/core/platform/terasic_c5g.

commit 3215511302e9138acc2880332f44f03863df17f6
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Fri May 9 13:19:01 2014 +0200

    Adding new prebuilt FPGA with uart that supports change of bitrate.
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 .../cryptech_pre_build_image/coretest_hashes.sof   | Bin 3993967 -> 3993967 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof
index d4880f2..d223599 100644
Binary files a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof and b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_hashes.sof differ