[Cryptech-Commits] [staging/core/rng/trng] 25/30: Updating testbenches to match new interfaces and use the api to read and write data.
git at cryptech.is
git at cryptech.is
Tue Mar 17 13:19:14 UTC 2015
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch master
in repository staging/core/rng/trng.
commit fe96fc8106b88b26311a5f911f42c73c66b977d9
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Thu Oct 2 14:25:46 2014 +0200
Updating testbenches to match new interfaces and use the api to read and write data.
---
src/tb/tb_csprng.v | 147 ++++++++++++++++++++++++++++++++++++--------------
src/tb/tb_mixer.v | 82 +++++++++++++++++++++++++++-
src/tb/tb_trng.v | 154 +++++++++++++++++++++++++++++++++++++++++++++++++----
3 files changed, 329 insertions(+), 54 deletions(-)
diff --git a/src/tb/tb_csprng.v b/src/tb/tb_csprng.v
index 10a7992..e92828d 100644
--- a/src/tb/tb_csprng.v
+++ b/src/tb/tb_csprng.v
@@ -65,21 +65,32 @@ module tb_csprng();
reg tb_clk;
reg tb_reset_n;
- reg tb_debug_mode;
- reg [4 : 0] tb_num_rounds;
- reg [63 : 0] tb_num_blocks;
- reg tb_seed;
- reg tb_enable;
+
+ reg tb_cs;
+ reg tb_we;
+ reg [7 : 0] tb_address;
+ reg [31 : 0] tb_write_data;
+ wire [31 : 0] tb_read_data;
+ wire tb_error;
+
+ reg tb_discard;
+ reg tb_test_mode;
+
wire tb_ready;
wire tb_more_seed;
- wire tb_error;
+ wire tb_security_error;
reg tb_seed_syn;
reg [511 : 0] tb_seed_data;
wire tb_seed_ack;
- wire tb_rnd_syn;
wire [31: 0] tb_rnd_data;
+ wire tb_rnd_syn;
reg tb_rnd_ack;
+ wire [7 : 0] tb_debug;
+ reg tb_debug_update;
+
+ reg [31 : 0] read_data;
+
//----------------------------------------------------------------
// Device Under Test.
@@ -88,22 +99,25 @@ module tb_csprng();
.clk(tb_clk),
.reset_n(tb_reset_n),
- .debug_mode(tb_debug_mode),
- .num_rounds(tb_num_rounds),
- .num_blocks(tb_num_blocks),
- .seed(tb_seed),
- .enable(tb_enable),
- .more_seed(tb_more_seed),
- .ready(tb_ready),
+ .cs(tb_cs),
+ .we(tb_we),
+ .address(tb_address),
+ .write_data(tb_write_data),
+ .read_data(tb_read_data),
.error(tb_error),
- .seed_syn(tb_seed_syn),
+ .discard(tb_discard),
+ .test_mode(tb_test_mode),
+
+ .more_seed(tb_more_seed),
+ .security_error(tb_security_error),
+
.seed_data(tb_seed_data),
+ .seed_syn(tb_seed_syn),
.seed_ack(tb_seed_ack),
- .rnd_syn(tb_rnd_syn),
- .rnd_data(tb_rnd_data),
- .rnd_ack(tb_rnd_ack)
+ .debug(tb_debug),
+ .debug_update(tb_debug_update)
);
@@ -149,12 +163,10 @@ module tb_csprng();
$display("State of DUT");
$display("------------");
$display("Inputs:");
- $display("debug_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x",
- dut.debug_mode, dut.seed, dut.enable);
- $display("ready = 0x%01x, error = 0x%01x",
- dut.ready, dut.error);
+ $display("test_mode = 0x%01x, seed = 0x%01x, enable = 0x%01x",
+ dut.test_mode, dut.seed_reg, dut.enable_reg);
$display("num_rounds = 0x%02x, num_blocks = 0x%016x",
- dut.num_rounds, dut.num_blocks);
+ dut.num_rounds_reg, dut.num_blocks);
$display("seed_syn = 0x%01x, seed_ack = 0x%01x, seed_data = 0x%064x",
dut.seed_syn, dut.seed_ack, dut.seed_data);
$display("");
@@ -190,6 +202,56 @@ module tb_csprng();
//----------------------------------------------------------------
+ // write_word()
+ //
+ // Write the given word to the DUT using the DUT interface.
+ //----------------------------------------------------------------
+ task write_word(input [11 : 0] address,
+ input [31 : 0] word);
+ begin
+ if (DEBUG)
+ begin
+ $display("*** Writing 0x%08x to 0x%02x.", word, address);
+ $display("");
+ end
+
+ tb_address = address;
+ tb_write_data = word;
+ tb_cs = 1;
+ tb_we = 1;
+ #(2 * CLK_PERIOD);
+ tb_cs = 0;
+ tb_we = 0;
+ end
+ endtask // write_word
+
+
+ //----------------------------------------------------------------
+ // read_word()
+ //
+ // Read a data word from the given address in the DUT.
+ // the word read will be available in the global variable
+ // read_data.
+ //----------------------------------------------------------------
+ task read_word(input [11 : 0] address);
+ begin
+ tb_address = address;
+ tb_cs = 1;
+ tb_we = 0;
+ #(CLK_PERIOD);
+ read_data = tb_read_data;
+ tb_cs = 0;
+
+ if (DEBUG)
+ begin
+ $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
+ $display("");
+ end
+ end
+ endtask // read_word
+
+
+ //----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
@@ -234,20 +296,25 @@ module tb_csprng();
//----------------------------------------------------------------
task init_sim();
begin
- cycle_ctr = 0;
- error_ctr = 0;
- tc_ctr = 0;
-
- tb_clk = 0;
- tb_reset_n = 1;
- tb_debug_mode = 0;
- tb_num_rounds = 5'h00;
- tb_num_blocks = 64'h0000000000000000;
- tb_seed = 0;
- tb_enable = 0;
- tb_seed_syn = 0;
- tb_seed_data = {16{32'h00000000}};
- tb_rnd_ack = 0;
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
+
+ tb_cs = 0;
+ tb_we = 0;
+ tb_address = 8'h00;
+ tb_write_data = 32'h00000000;
+
+ tb_discard = 0;
+ tb_test_mode = 0;
+
+ tb_seed_syn = 0;
+ tb_seed_data = {16{32'h00000000}};
+ tb_rnd_ack = 0;
+ tb_debug_update = 0;
end
endtask // init_sim
@@ -261,11 +328,9 @@ module tb_csprng();
task tc1_test_init_cipher();
begin
$display("*** TC1: Test automatic init of cipher started.");
- tb_num_blocks = 64'h0000000000000004;
- tb_seed_syn = 1;
+ // tb_num_blocks = 64'h0000000000000004;
tb_seed_data = {8{64'haaaaaaaa55555555}};
- tb_enable = 1;
- tb_num_rounds = 5'h08;
+ // tb_num_rounds = 5'h08;
tb_rnd_ack = 1;
#(2000 * CLK_PERIOD);
diff --git a/src/tb/tb_mixer.v b/src/tb/tb_mixer.v
index b08533a..3964197 100644
--- a/src/tb/tb_mixer.v
+++ b/src/tb/tb_mixer.v
@@ -66,7 +66,18 @@ module tb_mixer();
reg tb_clk;
reg tb_reset_n;
reg tb_enable;
+
+ reg tb_cs;
+ reg tb_we;
+ reg [7 : 0] tb_address;
+ reg [31 : 0] tb_write_data;
+ wire [31 : 0] tb_read_data;
+ wire tb_error;
+
+ reg tb_discard;
+ reg tb_test_mode;
reg tb_more_seed;
+ wire tb_security_error;
reg tb_entropy0_enabled;
reg tb_entropy0_syn;
@@ -87,6 +98,8 @@ module tb_mixer();
wire tb_syn;
reg tb_ack;
+ reg [31 : 0] read_data;
+
//----------------------------------------------------------------
// Device Under Test.
@@ -95,7 +108,17 @@ module tb_mixer();
.clk(tb_clk),
.reset_n(tb_reset_n),
- .enable(tb_enable),
+ .cs(tb_cs),
+ .we(tb_we),
+ .address(tb_address),
+ .write_data(tb_write_data),
+ .read_data(tb_read_data),
+ .error(tb_error),
+
+ .discard(tb_discard),
+ .test_mode(tb_test_mode),
+ .security_error(tb_security_error),
+
.more_seed(tb_more_seed),
.entropy0_enabled(tb_entropy0_enabled),
@@ -166,6 +189,56 @@ module tb_mixer();
//----------------------------------------------------------------
+ // write_word()
+ //
+ // Write the given word to the DUT using the DUT interface.
+ //----------------------------------------------------------------
+ task write_word(input [11 : 0] address,
+ input [31 : 0] word);
+ begin
+ if (DEBUG)
+ begin
+ $display("*** Writing 0x%08x to 0x%02x.", word, address);
+ $display("");
+ end
+
+ tb_address = address;
+ tb_write_data = word;
+ tb_cs = 1;
+ tb_we = 1;
+ #(2 * CLK_PERIOD);
+ tb_cs = 0;
+ tb_we = 0;
+ end
+ endtask // write_word
+
+
+ //----------------------------------------------------------------
+ // read_word()
+ //
+ // Read a data word from the given address in the DUT.
+ // the word read will be available in the global variable
+ // read_data.
+ //----------------------------------------------------------------
+ task read_word(input [11 : 0] address);
+ begin
+ tb_address = address;
+ tb_cs = 1;
+ tb_we = 0;
+ #(CLK_PERIOD);
+ read_data = tb_read_data;
+ tb_cs = 0;
+
+ if (DEBUG)
+ begin
+ $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
+ $display("");
+ end
+ end
+ endtask // read_word
+
+
+ //----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
@@ -216,8 +289,13 @@ module tb_mixer();
tb_clk = 0;
tb_reset_n = 1;
+ tb_cs = 0;
+ tb_we = 0;
+ tb_address = 8'h00;
+ tb_write_data = 32'h00000000;
- tb_enable = 0;
+ tb_discard = 0;
+ tb_test_mode = 0;
tb_more_seed = 0;
tb_entropy0_enabled = 0;
diff --git a/src/tb/tb_trng.v b/src/tb/tb_trng.v
index 704d4ea..38d2559 100644
--- a/src/tb/tb_trng.v
+++ b/src/tb/tb_trng.v
@@ -55,6 +55,49 @@ module tb_trng();
parameter CLK_HALF_PERIOD = 1;
parameter CLK_PERIOD = 2 * CLK_HALF_PERIOD;
+ // The DUT address map.
+ parameter TRNG_PREFIX = 4'h0;
+ parameter ENTROPY1_PREFIX = 4'h5;
+ parameter ENTROPY2_PREFIX = 4'h6;
+ parameter MIXER_PREFIX = 4'ha;
+ parameter CSPRNG_PREFIX = 4'hb;
+
+ parameter ADDR_TRNG_CTRL = 8'h10;
+ parameter TRNG_CTRL_ENABLE_BIT = 0;
+ parameter TRNG_CTRL_ENT0_ENABLE_BIT = 1;
+ parameter TRNG_CTRL_ENT1_ENABLE_BIT = 2;
+ parameter TRNG_CTRL_ENT2_ENABLE_BIT = 3;
+ parameter TRNG_CTRL_SEED_BIT = 8;
+
+ parameter ADDR_TRNG_STATUS = 8'h11;
+
+ parameter ADDR_TRNG_RND_DATA = 8'h20;
+ parameter ADDR_TRNG_RND_DATA_VALID = 8'h21;
+ parameter TRNG_RND_VALID_BIT = 0;
+
+ parameter ADDR_CSPRNG_CTRL = 8'h10;
+ parameter CSPRNG_CTRL_ENABLE_BIT = 0;
+ parameter CSPRNG_CTRL_SEED_BIT = 1;
+
+ parameter ADDR_CSPRNG_STATUS = 8'h11;
+ parameter CSPRNG_STATUS_RND_VALID_BIT = 0;
+
+ parameter ADDR_CSPRNG_NUM_ROUNDS = 8'h40;
+ parameter ADDR_CSPRNG_NUM_BLOCKS_LOW = 8'h41;
+ parameter ADDR_CSPRNG_NUM_BLOCKS_HIGH = 8'h42;
+
+ parameter ADDR_ENTROPY0_RAW = 8'h40;
+ parameter ADDR_ENTROPY0_STATS = 8'h41;
+
+ parameter ADDR_ENTROPY1_RAW = 8'h50;
+ parameter ADDR_ENTROPY1_STATS = 8'h51;
+
+ parameter ADDR_ENTROPY2_RAW = 8'h60;
+ parameter ADDR_ENTROPY2_STATS = 8'h61;
+
+ parameter ADDR_MIXER_CTRL = 8'h10;
+ parameter MIXER_CTRL_ENABLE_BIT = 0;
+ parameter MIXER_CTRL_RESTART_BIT = 1;
//----------------------------------------------------------------
// Register and Wire declarations.
@@ -63,14 +106,18 @@ module tb_trng();
reg [31 : 0] error_ctr;
reg [31 : 0] tc_ctr;
+ reg [31 : 0] read_data;
+
reg tb_clk;
reg tb_reset_n;
reg tb_avalanche_noise;
reg tb_cs;
reg tb_we;
- reg [7 : 0] tb_address;
+ reg [11 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
+ wire [7 : 0] tb_debug;
+ reg tb_debug_update;
wire tb_error;
wire tb_security_error;
@@ -79,7 +126,7 @@ module tb_trng();
// Device Under Test.
//----------------------------------------------------------------
trng dut(
- .clk(tb_ckl),
+ .clk(tb_clk),
.reset_n(tb_reset_n),
.avalanche_noise(tb_avalanche_noise),
.cs(tb_cs),
@@ -88,11 +135,18 @@ module tb_trng();
.write_data(tb_write_data),
.read_data(tb_read_data),
.error(tb_error),
+ .debug(tb_debug),
+ .debug_update(tb_debug_update),
.security_error(tb_security_error)
);
//----------------------------------------------------------------
+ // Concurrent assignments.
+ //----------------------------------------------------------------
+
+
+ //----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
@@ -139,6 +193,56 @@ module tb_trng();
//----------------------------------------------------------------
+ // write_word()
+ //
+ // Write the given word to the DUT using the DUT interface.
+ //----------------------------------------------------------------
+ task write_word(input [11 : 0] address,
+ input [31 : 0] word);
+ begin
+ if (DEBUG)
+ begin
+ $display("*** Writing 0x%08x to 0x%02x.", word, address);
+ $display("");
+ end
+
+ tb_address = address;
+ tb_write_data = word;
+ tb_cs = 1;
+ tb_we = 1;
+ #(2 * CLK_PERIOD);
+ tb_cs = 0;
+ tb_we = 0;
+ end
+ endtask // write_word
+
+
+ //----------------------------------------------------------------
+ // read_word()
+ //
+ // Read a data word from the given address in the DUT.
+ // the word read will be available in the global variable
+ // read_data.
+ //----------------------------------------------------------------
+ task read_word(input [11 : 0] address);
+ begin
+ tb_address = address;
+ tb_cs = 1;
+ tb_we = 0;
+ #(CLK_PERIOD);
+ read_data = tb_read_data;
+ tb_cs = 0;
+
+ if (DEBUG)
+ begin
+ $display("*** Reading 0x%08x from 0x%02x.", read_data, address);
+ $display("");
+ end
+ end
+ endtask // read_word
+
+
+ //----------------------------------------------------------------
// reset_dut()
//
// Toggle reset to put the DUT into a well known state.
@@ -183,13 +287,19 @@ module tb_trng();
//----------------------------------------------------------------
task init_sim();
begin
- cycle_ctr = 0;
- error_ctr = 0;
- tc_ctr = 0;
-
- tb_clk = 0;
- tb_reset_n = 1;
-
+ cycle_ctr = 0;
+ error_ctr = 0;
+ tc_ctr = 0;
+
+ tb_clk = 0;
+ tb_reset_n = 1;
+
+ tb_avalanche_noise = 0;
+ tb_cs = 0;
+ tb_we = 0;
+ tb_address = 12'h000;
+ tb_write_data = 32'h00000000;
+ tb_debug_update = 0;
end
endtask // init_sim
@@ -198,15 +308,37 @@ module tb_trng();
// tc1_gen_rnd()
//
// A simple first testcase that tries to make the DUT generate
- // a number of seeds based on entropy from source 0 and 2.
+ // a number of random values.
//----------------------------------------------------------------
task tc1_gen_rnd();
+ reg [31 : 0] i;
+
begin
$display("*** Starting TC1: Generating random values from entropy.");
+ tb_debug_update = 1;
- #(50000 * CLK_PERIOD);
+ #(10 * CLK_PERIOD);
+ // Enable the csprng and the mixer
+ write_word({CSPRNG_PREFIX, ADDR_CSPRNG_CTRL}, 32'h00000001);
+ write_word({MIXER_PREFIX, ADDR_MIXER_CTRL}, 32'h00000001);
+
+
+ // We try to change number of blocks to a low value to force reseeding.
+ write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_LOW}, 32'h00000002);
+ write_word({CSPRNG_PREFIX, ADDR_CSPRNG_NUM_BLOCKS_HIGH}, 32'h00000000);
+
+ #(100 * CLK_PERIOD);
+
+ i = 0;
+ while (i < 100000)
+ begin
+ $display("Reading rnd word %08x.", i);
+ i = i + 1;
+ read_word({CSPRNG_PREFIX, ADDR_TRNG_RND_DATA});
+ #(2 * CLK_PERIOD);
+ end
$display("*** TC1 done.");
end
More information about the Commits
mailing list