[Cryptech-Commits] [staging/core/rng/trng] 22/30: Adding debug port for mixer and csprng. In the csprng the debug_update will trigger fifo extraction and thus force random number generation.

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paul at psgd.org pushed a commit to branch master
in repository staging/core/rng/trng.

commit 821471932eb48bb39a820fc6680355231e6093fa
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sat Sep 27 14:38:05 2014 +0200

    Adding debug port for mixer and csprng. In the csprng the debug_update will trigger fifo extraction and thus force random number generation.
---
 src/rtl/trng.v        | 28 ++++++++++++++++++++++++++--
 src/rtl/trng_csprng.v |  7 +++++--
 src/rtl/trng_mixer.v  |  7 ++++++-
 3 files changed, 37 insertions(+), 5 deletions(-)

diff --git a/src/rtl/trng.v b/src/rtl/trng.v
index f00aa79..7d0e45d 100644
--- a/src/rtl/trng.v
+++ b/src/rtl/trng.v
@@ -119,6 +119,8 @@ module trng(
   reg            mixer_api_we;
   wire [31 : 0]  mixer_api_read_data;
   wire           mixer_api_error;
+  wire [7 : 0]   mixer_debug;
+  reg            mixer_debug_update;
 
   wire           csprng_more_seed;
   wire           csprng_seed_ack;
@@ -126,6 +128,8 @@ module trng(
   reg            csprng_api_we;
   wire [31 : 0]  csprng_api_read_data;
   wire           csprng_api_error;
+  wire [7 : 0]   csprng_debug;
+  reg            csprng_debug_update;
 
   wire           entropy0_entropy_enabled;
   wire [31 : 0]  entropy0_entropy_data;
@@ -214,7 +218,10 @@ module trng(
 
                    .seed_data(mixer_seed_data),
                    .seed_syn(mixer_seed_syn),
-                   .seed_ack(csprng_seed_ack)
+                   .seed_ack(csprng_seed_ack),
+
+                   .debug(mixer_debug),
+                   .debug_update(mixer_debug_update)
                   );
 
   trng_csprng csprng(
@@ -235,7 +242,10 @@ module trng(
 
                      .seed_data(mixer_seed_data),
                      .seed_syn(mixer_seed_syn),
-                     .seed_ack(csprng_seed_ack)
+                     .seed_ack(csprng_seed_ack),
+
+                     .debug(csprng_debug),
+                     .debug_update(csprng_debug_update)
                     );
 
   avalanche_entropy entropy1(
@@ -328,6 +338,8 @@ module trng(
     begin : debug_mux
       entropy1_debug_update = 0;
       entropy2_debug_update = 0;
+      mixer_debug_update    = 0;
+      csprng_debug_update   = 0;
 
       tmp_debug = 8'h00;
 
@@ -344,6 +356,18 @@ module trng(
             tmp_debug             = entropy2_debug;
           end
 
+        DEBUG_MIXER:
+          begin
+            mixer_debug_update = debug_update;
+            tmp_debug          = mixer_debug;
+          end
+
+        DEBUG_CSPRNG:
+          begin
+            csprng_debug_update = debug_update;
+            tmp_debug           = csprng_debug;
+          end
+
         default:
           begin
 
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index a6dd247..83c383f 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -178,6 +178,8 @@ module trng_csprng(
 
   wire [63 : 0]  num_blocks;
 
+  wire           muxed_rnd_ack;
+
 
   //----------------------------------------------------------------
   // Concurrent connectivity for ports etc.
@@ -186,10 +188,11 @@ module trng_csprng(
   assign error          = tmp_error;
   assign seed_ack       = seed_ack_reg;
   assign more_seed      = more_seed_reg;
-  assign debug          = 8'haa;
+  assign debug          = rnd_data[7 : 0];
   assign security_error = 0;
 
   assign num_blocks     = {num_blocks_high_reg, num_blocks_low_reg};
+  assign muxed_rnd_ack  = rnd_ack | debug_update;
 
 
   //----------------------------------------------------------------
@@ -227,7 +230,7 @@ module trng_csprng(
 
                         .rnd_syn(rnd_syn),
                         .rnd_data(rnd_data),
-                        .rnd_ack(rnd_ack)
+                        .rnd_ack(muxed_rnd_ack)
                        );
 
 
diff --git a/src/rtl/trng_mixer.v b/src/rtl/trng_mixer.v
index 7d398f5..d11050c 100644
--- a/src/rtl/trng_mixer.v
+++ b/src/rtl/trng_mixer.v
@@ -69,7 +69,10 @@ module trng_mixer(
 
                   output wire [511 : 0] seed_data,
                   output wire           seed_syn,
-                  input wire            seed_ack
+                  input wire            seed_ack,
+
+                  output wire [7 : 0]   debug,
+                  input wire            debug_update
                  );
 
 
@@ -246,6 +249,8 @@ module trng_mixer(
   assign entropy1_ack = tmp_entropy1_ack;
   assign entropy2_ack = tmp_entropy2_ack;
 
+  assign debug = 8'h55;
+
 
   //----------------------------------------------------------------
   // core instantiation.