[Cryptech-Commits] [staging/core/platform/terasic_c5g] 04/20: Updating address for uart to 8 bits which should be the default.

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paul at psgd.org pushed a commit to branch master
in repository staging/core/platform/terasic_c5g.

commit 9a275f837bedb527f0b637ce1dc20828baebc0c2
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Mon Mar 17 09:56:52 2014 +0100

    Updating address for uart to 8 bits which should be the default.
---
 src/rtl/coretest_hashes.v | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/rtl/coretest_hashes.v b/src/rtl/coretest_hashes.v
index 150f194..d3fda6a 100644
--- a/src/rtl/coretest_hashes.v
+++ b/src/rtl/coretest_hashes.v
@@ -80,7 +80,7 @@ module coretest_hashes(
   wire          uart_txd_ack;
   reg           uart_cs;
   reg           uart_we;
-  reg [3 : 0]   uart_address;
+  reg [7 : 0]   uart_address;
   reg [31 : 0]  uart_write_data;
   wire [31 : 0] uart_read_data;
   wire          uart_error;
@@ -211,7 +211,7 @@ module coretest_hashes(
 
       uart_cs            = 0;
       uart_we            = 0;
-      uart_address       = 4'h0;
+      uart_address       = 8'h00;
       uart_write_data    = 32'h00000000;
 
       sha1_cs            = 0;
@@ -230,7 +230,7 @@ module coretest_hashes(
           begin
             uart_cs            = coretest_cs;
             uart_we            = coretest_we;
-            uart_address       = coretest_address[3 : 0];
+            uart_address       = coretest_address[7 : 0];
             uart_write_data    = coretest_write_data;
             coretest_read_data = uart_read_data;
             coretest_error     = uart_error;