[Cryptech-Commits] [staging/core/hash/sha256] 18/32: Update or README with more info on status.

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paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha256.

commit 88dd849e565316fc57ce7627abc203fe2648a36a
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sun Feb 23 22:10:44 2014 +0100

    Update or README with more info on status.
---
 README.md | 37 ++++++++++++++++++-------------------
 1 file changed, 18 insertions(+), 19 deletions(-)

diff --git a/README.md b/README.md
index 1171832..b5fcd12 100644
--- a/README.md
+++ b/README.md
@@ -23,41 +23,40 @@ inserted at r15 as well as being returned to the core.
 ### Cyclone IV E ###
 Implementation results using the Altera Quartus-II v13.1 design tool.
 
-Device: Cyclone IV E - EP4CE6F17C6
-- 3765 LEs
+***Cyclone IV E***
+- EP4CE6F17C6
+- 3882 LEs
 - 1813 registers
-- 76 MHz
+- 74 MHz
 - 66 cycles latency
 
-
-### Cyclone IV GX ###
-Implementation results using the Altera Quartus-II v13.1 design tool.
-
-Device: Cyclone IV GX - EP4CGX22CF19C6
-- 3765 LEs
+***Cyclone IV GX***
+- EP4CGX22CF19C6
+- 3773 LEs
 - 1813 registers
 - 76 MHz
 - 66 cycles latency
 
-
-### Cyclone V GX ###
-Implementation results using the Altera Quartus-II v13.1 design tool.
-
-Device: Cyclone V GX - 5CGXFC7C7F23C8
-- 1456 ALMs
+***Cyclone V***
+- 5CGXFC7C7F23C8
+- 1469 ALMs
 - 1813 registers
-- 78 MHz
+- 79 MHz
 - 66 cycles latency
 
 
-
-
-## Todo ##
+## TODO ##
 - Extensive verification in physical device.
 - Complete documentation.
 
 
 ## Status ##
+***(2013-02-23)***
+
+Cleanup, more results etc. Move all wmem update logic to a separate
+process for a cleaner code.
+
+
 **(2014-02-22)**
 
 Redesigned the W-memory into a sliding window solution. This not only