[Cryptech-Commits] [staging/core/comm/uart] 10/13: Update of core address size to 8 bits. Changed use of bit rate, data and stop bits from the top.
git at cryptech.is
git at cryptech.is
Tue Mar 17 13:13:44 UTC 2015
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paul at psgd.org pushed a commit to branch master
in repository staging/core/comm/uart.
commit 01c483ae3f75ac6c4f46425581f0900f99f60109
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri May 9 13:12:24 2014 +0200
Update of core address size to 8 bits. Changed use of bit rate, data and stop bits from the top.
---
src/tb/tb_uart.v | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/src/tb/tb_uart.v b/src/tb/tb_uart.v
index 20a390e..1abdd34 100644
--- a/src/tb/tb_uart.v
+++ b/src/tb/tb_uart.v
@@ -72,7 +72,7 @@ module tb_uart();
wire tb_txd_ack;
reg tb_cs;
reg tb_we;
- reg [3 : 0] tb_address;
+ reg [7 : 0] tb_address;
reg [31 : 0] tb_write_data;
wire [31 : 0] tb_read_data;
wire tb_error;
@@ -265,7 +265,7 @@ module tb_uart();
tb_rxd = 1;
tb_cs = 0;
tb_we = 0;
- tb_address = 4'h0;
+ tb_address = 8'h00;
tb_write_data = 32'h00000000;
txd_state = 1;
@@ -288,20 +288,20 @@ module tb_uart();
// Start bit
$display("*** Transmitting start bit.");
tb_rxd = 0;
- #(CLK_PERIOD * dut.core.DEFAULT_CLK_RATE);
+ #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
// Send the bits LSB first.
for (i = 0 ; i < 8 ; i = i + 1)
begin
$display("*** Transmitting data[%1d] = 0x%01x.", i, data[i]);
tb_rxd = data[i];
- #(CLK_PERIOD * dut.core.DEFAULT_CLK_RATE);
+ #(CLK_PERIOD * dut.DEFAULT_BIT_RATE);
end
// Send two stop bits. I.e. two bit times high (mark) value.
$display("*** Transmitting two stop bits.");
tb_rxd = 1;
- #(2 * CLK_PERIOD * dut.core.DEFAULT_CLK_RATE * dut.core.DEFAULT_STOP_BITS);
+ #(2 * CLK_PERIOD * dut.DEFAULT_BIT_RATE * dut.DEFAULT_STOP_BITS);
$display("*** End of transmission.");
end
endtask // transmit_byte
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