[Cryptech-Commits] [staging/core/hash/sha256] branch master created (now 4b63312)

[git at cryptech.is]

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paul at psgd.org pushed a change to branch master
in repository staging/core/hash/sha256.

        at  4b63312   Rearrange cores.

This branch includes the following new commits:

       new  5d2bb32   Adding license description for the sha256 core.
       new  7a240ee   Adding makefile for building and simulating the sha256 design.
       new  ec9e72b   Adding K constant memory source file.
       new  3aa7a8f   Adding the W memory including scheduler and expansion functionality.
       new  3ed428f   Source for the main part of the sha256 core.
       new  8ea622d   Adding top level wrapper for the sha256. This wrapper provides a simple memory like interface.
       new  665fe30   Adding a Wishbone wrapper for the SHA256 core.
       new  7a32199   Adding a testbench for the w memory module.
       new  3daec51   Adding a testbench for the SHA256 core.
       new  4baf950   Adding a testbench for the SHA256 top level wrapper.
       new  6a9fef5   Adding a testbench for the Wishbone wrapper.
       new  41c4fbd   Adding a Python model for the SHA256 core.
       new  7340c6e   Adding a simple README file in markdown format that describes the core.
       new  c6e33cb   Changed W-memory into sliding window. This also affected interface and integration in the core.
       new  62ea7be   Updated testbenches to the new sliding window W-mem.
       new  9f03046   Updated status with info on the sliding window W-mem and the new implementation results.
       new  93b3b5f   Moved wmem update logic to a separate process.
       new  88dd849   Update or README with more info on status.
       new  b18e54e   Fixed compile problems due to copy crime.
       new  e242bbe   Updating README with info on the design.
       new  1991804   Adding more info about the core.
       new  588ce16   Changed the python model to use a sliding window for W.
       new  52c2f0b   Removed the positions of W no longer needed.
       new  6e8e124   (1) Updated interface to new std. (2) Added missing input designation in tasks. Now simumaltion with ModelSim works.
       new  c33d1df   Adding self resetting init and next flags. Updating TBs to not reset the flags. Fixing clock parameter naming.
       new  7725609   Removed redundant flag reset wires.
       new  f69f454   Updating sha256 python model with NIST dual block test case and test case with huge message. Disabling verbose mode.
       new  3c7c7c3   Adding helper functions for printing digest. Adding testcase for message with 1000 blocks.
       new  c4cd88c   Fixed nits found using verilator linter. Removed trailing whitespace.
       new  bbfa764   Changed to asynch reset.
       new  4b24edf   Removed the wishbone wrapper we don't use.
       new  4b63312   Rearrange cores.

The 32 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.