[Cryptech-Commits] [staging/core/rng/avalanche_entropy] 05/08: Updated headers.
git at cryptech.is
git at cryptech.is
Tue Mar 17 13:18:23 UTC 2015
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paul at psgd.org pushed a commit to branch master
in repository staging/core/rng/avalanche_entropy.
commit 5c11ddc6b954f1715f116c0820d2245f9747e67d
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri Sep 26 14:44:25 2014 +0200
Updated headers.
---
src/rtl/avalanche_entropy.v | 46 +++++------
src/rtl/avalanche_entropy_core.v | 174 ++++++++++++---------------------------
2 files changed, 75 insertions(+), 145 deletions(-)
diff --git a/src/rtl/avalanche_entropy.v b/src/rtl/avalanche_entropy.v
index a7a23b1..bc3a815 100644
--- a/src/rtl/avalanche_entropy.v
+++ b/src/rtl/avalanche_entropy.v
@@ -12,33 +12,33 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2013, 2014, Secworks Sweden AB
-// All rights reserved.
+// Copyright (c) 2014, NORDUnet A/S All rights reserved.
//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are
+// met:
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
-// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
-// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
diff --git a/src/rtl/avalanche_entropy_core.v b/src/rtl/avalanche_entropy_core.v
index 6269d04..5f217af 100644
--- a/src/rtl/avalanche_entropy_core.v
+++ b/src/rtl/avalanche_entropy_core.v
@@ -70,8 +70,7 @@ module avalanche_entropy_core(
parameter ADDR_ENTROPY = 8'h10;
parameter ADDR_DELTA = 8'h20;
- parameter LED_RATE = 32'h00300000;
- parameter SECONDS_RATE = 32'h02faf080;
+ parameter DEBUG_DELAY = 32'h002c4b40;
//----------------------------------------------------------------
@@ -97,21 +96,6 @@ module avalanche_entropy_core(
reg bit_ctr_inc;
reg bit_ctr_we;
- reg [3 : 0] debug_ctr_reg;
- reg [3 : 0] debug_ctr_new;
- reg debug_ctr_inc;
- reg debug_ctr_we;
-
- reg debug_clk_reg;
- reg debug_clk_new;
-
- reg [7 : 0] led_reg;
- reg [7 : 0] led_new;
- reg led_we;
-
- reg [31 : 0] led_ctr_reg;
- reg [31 : 0] led_ctr_new;
-
reg [31 : 0] cycle_ctr_reg;
reg [31 : 0] cycle_ctr_new;
@@ -121,12 +105,19 @@ module avalanche_entropy_core(
reg delta_clk_reg;
reg delta_clk_new;
+ reg [31 : 0] debug_delay_ctr_reg;
+ reg [31 : 0] debug_delay_ctr_new;
+ reg debug_delay_ctr_we;
+
+ reg [7 : 0] debug_reg;
+ reg debug_we;
+
+ reg debug_update_reg;
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
-// reg [31 : 0] tmp_read_data;
-// reg tmp_error;
//----------------------------------------------------------------
@@ -135,19 +126,14 @@ module avalanche_entropy_core(
assign entropy_syn = entropy_syn_reg;
assign entropy_data = entropy_reg;
- assign led = led_reg;
- assign debug_data = entropy_reg[7 : 0];
- assign debug_clk = debug_clk_reg;
-
assign sampled_noise = noise_sample_reg;
assign entropy = entropy_reg[0];
-// assign read_data = tmp_read_data;
-// assign error = tmp_error;
-
assign delta_data = delta_reg;
assign delta_clk = delta_clk_reg;
+ assign debug = debug_reg;
+
//----------------------------------------------------------------
// reg_update
@@ -164,13 +150,14 @@ module avalanche_entropy_core(
entropy_reg <= 32'h00000000;
entropy_bit_reg <= 1'b0;
bit_ctr_reg <= 6'h00;
- led_reg <= 8'h00;
- led_ctr_reg <= 32'h00000000;
debug_ctr_reg <= 4'h0;
debug_clk_reg <= 1'b0;
cycle_ctr_reg <= 32'h00000000;
delta_reg <= 32'h00000000;
delta_clk_reg <= 1'b0;
+ debug_delay_ctr_reg <= 32'h00000000;
+ debug_reg <= 8'h00;
+ debug_update_reg <= 0;
end
else
begin
@@ -180,16 +167,15 @@ module avalanche_entropy_core(
flank0_reg <= noise_sample_reg;
flank1_reg <= flank0_reg;
- entropy_syn_reg <= entropy_syn_new;
+ entropy_syn_reg <= entropy_syn_new;
entropy_bit_reg <= ~entropy_bit_reg;
- led_ctr_reg <= led_ctr_new;
- debug_clk_reg <= debug_clk_new;
-
delta_clk_reg <= delta_clk_new;
cycle_ctr_reg <= cycle_ctr_new;
+ debug_update_reg <= debug_update;
+
if (delta_we)
begin
delta_reg <= cycle_ctr_reg;
@@ -210,15 +196,46 @@ module avalanche_entropy_core(
entropy_reg <= entropy_new;
end
- if (led_we)
+ if (debug_delay_ctr_we)
begin
- led_reg <= entropy_reg[7 : 0];
+ debug_delay_ctr_reg <= debug_delay_ctr_new;
+ end
+
+ if (debug_we)
+ begin
+ debug_reg <= ent_shift_reg[7 : 0];
end
end
end // reg_update
//----------------------------------------------------------------
+ // debug_out
+ //
+ // Logic that updates the debug port.
+ //----------------------------------------------------------------
+ always @*
+ begin : debug_out
+ debug_delay_ctr_new = 32'h00000000;
+ debug_delay_ctr_we = 0;
+ debug_we = 0;
+
+ if (debug_update_reg)
+ begin
+ debug_delay_ctr_new = debug_delay_ctr_reg + 1'b1;
+ debug_delay_ctr_we = 1;
+ end
+
+ if (debug_delay_ctr_reg == DEBUG_DELAY)
+ begin
+ debug_delay_ctr_new = 32'h00000000;
+ debug_delay_ctr_we = 1;
+ debug_we = 1;
+ end
+ end
+
+
+ //----------------------------------------------------------------
// entropy_collect
//
// We collect entropy by adding the current state of the
@@ -274,7 +291,7 @@ module avalanche_entropy_core(
debug_ctr_we = 0;
debug_clk_new = 0;
- if (debug_ctr_reg == 4'h08)
+ if (debug_ctr_reg == 4'h8)
begin
debug_ctr_new = 4'h0;
debug_ctr_we = 1;
@@ -318,93 +335,6 @@ module avalanche_entropy_core(
end
end // entropy_ack_logic
-
- //----------------------------------------------------------------
- // led_update
- //
- // Sample the entropy register as LED output value at
- // the given LED_RATE.
- //----------------------------------------------------------------
- always @*
- begin : led_update
- led_ctr_new = led_ctr_reg + 1'b1;
- led_we = 1'b0;
-
- if (led_ctr_reg == LED_RATE)
- begin
- led_ctr_new = 32'h00000000;
- led_we = 1'b1;
- end
- end // led_update
-
-
- //----------------------------------------------------------------
- // api_logic
- //----------------------------------------------------------------
-// always @*
-// begin : api_logic
-// tmp_read_data = 32'h00000000;
-// tmp_error = 1'b0;
-// bit_ctr_rst = 1'b1;
-//
-// if (cs)
-// begin
-// if (we)
-// begin
-// case (address)
-// // Write operations.
-//
-// default:
-// begin
-// tmp_error = 1;
-// end
-// endcase // case (address)
-// end // if (we)
-//
-// else
-// begin
-// case (address)
-// // Read operations.
-// ADDR_STATUS:
-// begin
-// tmp_read_data = {31'h00000000, entropy_syn_reg};
-// end
-//
-// ADDR_ENTROPY:
-// begin
-// tmp_read_data = entropy_reg;
-// bit_ctr_rst = 1'b1;
-// end
-//
-// ADDR_POS_FLANKS:
-// begin
-// tmp_read_data = posflank_sample_reg;
-// end
-//
-// ADDR_NEG_FLANKS:
-// begin
-// tmp_read_data = negflank_sample_reg;
-// end
-//
-// ADDR_TOT_FLANKS:
-// begin
-// tmp_read_data = totflank_sample_reg;
-// end
-//
-// ADDR_DELTA:
-// begin
-// tmp_read_data = delta_reg;
-// end
-//
-// default:
-// begin
-// tmp_error = 1;
-// end
-// endcase // case (address)
-// end // else: !if(we)
-// end // if (cs)
-// end // api_logic
-
endmodule // avalanche_entropy_core
//======================================================================
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