[Cryptech-Commits] [staging/core/hash/sha1] 17/20: Adding API table.

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paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha1.

commit d09b5ae4075e117ccf4d470050941fc2cd9da268
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Fri Nov 7 15:16:00 2014 +0100

    Adding API table.
---
 README.md | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)

diff --git a/README.md b/README.md
index 69dde95..f7eac7f 100644
--- a/README.md
+++ b/README.md
@@ -30,6 +30,42 @@ interface with 32-bit data access . This interface contains mesage block
 and digest registers to allow a host to load the next block while the
 current block is being processed.
 
+## API ##
+The following list contains the address map for all registers
+implemented by the sha1 top level wrapper:
+
+| address | name     | access | description                                     |
+|---------|----------|--------|-------------                                    |
+| 0x00    | name0    |   R    |  "SHA1"                                         |
+| 0x01    | name1    |   R    |  "    "                                         |
+| 0x02    | version  |   R    |  "0.50"                                         |
+|         |          |        |                                                 |
+| 0x08    | control  |  R/W   | Control of core. Bit 0: init, Bit 1: next       |
+| 0x09    | status   |  R/W   | Status of core. Bit 0: Ready, Bit 1: valid data |
+|         |          |        |                                                 |
+| 0x10    | block0   |  R/W   | data block register                             |
+| 0x11    | block1   |  R/W   | data block register                             |
+| 0x12    | block2   |  R/W   | data block register                             |
+| 0x13    | block3   |  R/W   | data block register                             |
+| 0x14    | block4   |  R/W   | data block register                             |
+| 0x15    | block5   |  R/W   | data block register                             |
+| 0x16    | block6   |  R/W   | data block register                             |
+| 0x17    | block7   |  R/W   | data block register                             |
+| 0x18    | block8   |  R/W   | data block register                             |
+| 0x19    | block9   |  R/W   | data block register                             |
+| 0x1a    | block10  |  R/W   | data block register                             |
+| 0x1b    | block11  |  R/W   | data block register                             |
+| 0x1c    | block12  |  R/W   | data block register                             |
+| 0x1d    | block13  |  R/W   | data block register                             |
+| 0x1e    | block14  |  R/W   | data block register                             |
+| 0x1f    | block15  |  R/W   | data block register                             |
+|         |          |        |                                                 |
+| 0x20    | digest0  |  R/W   | digest register                                 |
+| 0x21    | digest1  |  R/W   | digest register                                 |
+| 0x22    | digest2  |  R/W   | digest register                                 |
+| 0x23    | digest3  |  R/W   | digest register                                 |
+| 0x24    | digest4  |  R/W   | digest register                                 |
+
 
 ## Implementation details ##
 The implementation is iterative with one cycle/round. The initialization