[Cryptech-Commits] [staging/core/hash/sha1] 11/20: Added wait to allow the ready flag to be dropped with resettable flags. Fixed name of clock delay parameter.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha1.

commit af4e88047d524f2d0b43402e51476fa1932efe95
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sun Mar 16 21:34:52 2014 +0100

    Added wait to allow the ready flag to be dropped with resettable flags. Fixed name of clock delay parameter.
---
 src/tb/tb_sha1.v      | 16 +++++++++-------
 src/tb/tb_sha1_core.v | 16 +++++++++-------
 2 files changed, 18 insertions(+), 14 deletions(-)

diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v
index 6e39075..abf25d2 100644
--- a/src/tb/tb_sha1.v
+++ b/src/tb/tb_sha1.v
@@ -5,6 +5,7 @@
 // Testbench for the SHA-1 top level wrapper.
 //
 //
+// Author: Joachim Strombergson
 // Copyright (c) 2014, SUNET
 // All rights reserved.
 // 
@@ -48,7 +49,8 @@ module tb_sha1();
   parameter DEBUG_CORE = 0;
   parameter DEBUG_TOP  = 0;
 
-  parameter CLK_HALF_PERIOD = 2;
+  parameter CLK_HALF_PERIOD = 1;
+  parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
   
   parameter ADDR_NAME0       = 8'h00;
   parameter ADDR_NAME1       = 8'h01;
@@ -150,7 +152,7 @@ module tb_sha1();
           dump_top_state();
         end
 
-      #(2 * CLK_HALF_PERIOD);
+      #(CLK_PERIOD);
       cycle_ctr = cycle_ctr + 1;
     end
 
@@ -333,7 +335,7 @@ module tb_sha1();
       tb_address = address;
       tb_cs = 1;
       tb_write_read = 0;
-      #(2 * CLK_HALF_PERIOD);
+      #(CLK_PERIOD);
       read_data = tb_data_out;
       tb_cs = 0;
 
@@ -364,7 +366,7 @@ module tb_sha1();
       tb_data_in = word;
       tb_cs = 1;
       tb_write_read = 1;
-      #(2 * CLK_HALF_PERIOD);
+      #(CLK_PERIOD);
       tb_cs = 0;
       tb_write_read = 0;
     end
@@ -461,7 +463,7 @@ module tb_sha1();
      
       write_block(block);
       write_word(ADDR_CTRL, CTRL_INIT_VALUE);
-      write_word(ADDR_CTRL, 8'h00);
+      #(CLK_PERIOD);
       wait_ready();
       read_digest();
 
@@ -500,7 +502,7 @@ module tb_sha1();
       // First block
       write_block(block0);
       write_word(ADDR_CTRL, CTRL_INIT_VALUE);
-      write_word(ADDR_CTRL, 8'h00);
+      #(CLK_PERIOD);
       wait_ready();
       read_digest();
 
@@ -519,7 +521,7 @@ module tb_sha1();
       // Final block
       write_block(block1);
       write_word(ADDR_CTRL, CTRL_NEXT_VALUE);
-      write_word(ADDR_CTRL, 8'h00);
+      #(CLK_PERIOD);
       wait_ready();
       read_digest();
       
diff --git a/src/tb/tb_sha1_core.v b/src/tb/tb_sha1_core.v
index 8a5d11b..0ae592d 100644
--- a/src/tb/tb_sha1_core.v
+++ b/src/tb/tb_sha1_core.v
@@ -6,7 +6,8 @@
 //
 //
 // Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
+// All rights reserved.
 // 
 // Redistribution and use in source and binary forms, with or 
 // without modification, are permitted provided that the following 
@@ -47,7 +48,8 @@ module tb_sha1_core();
   //----------------------------------------------------------------
   parameter DEBUG = 0;
 
-  parameter CLK_HALF_PERIOD = 2;
+  parameter CLK_HALF_PERIOD = 1;
+  parameter CLK_PERIOD = CLK_HALF_PERIOD * 2;
   
   
   //----------------------------------------------------------------
@@ -103,7 +105,7 @@ module tb_sha1_core();
   //----------------------------------------------------------------
   always
     begin : sys_monitor
-      #(2 * CLK_HALF_PERIOD);
+      #(CLK_PERIOD);
       if (DEBUG)
         begin
           dump_dut_state();
@@ -225,7 +227,7 @@ module tb_sha1_core();
     begin
       while (!tb_ready)
         begin
-          #(2 * CLK_HALF_PERIOD);
+          #(CLK_PERIOD);
           
         end
     end
@@ -246,7 +248,7 @@ module tb_sha1_core();
 
      tb_block = block;
      tb_init = 1;
-     #(2 * CLK_HALF_PERIOD);
+     #(CLK_PERIOD);
      tb_init = 0;
      wait_ready();
 
@@ -290,7 +292,7 @@ module tb_sha1_core();
      $display("*** TC %0d first block started.", tc_number);
      tb_block = block1;
      tb_init = 1;
-     #(2 * CLK_HALF_PERIOD);
+     #(CLK_PERIOD);
      tb_init = 0;
      wait_ready();
      db_digest1 = tb_digest;
@@ -299,7 +301,7 @@ module tb_sha1_core();
      $display("*** TC %0d second block started.", tc_number);
      tb_block = block2;
      tb_next = 1;
-     #(2 * CLK_HALF_PERIOD);
+     #(CLK_PERIOD);
      tb_next = 0;
      wait_ready();
      $display("*** TC %0d second block done.", tc_number);