[Cryptech-Commits] [staging/core/hash/sha1] 10/20: Updating interface. Addding self resetting control regs. Fixing missing input port declaration that caused errors during simulation in ModelSim.
git at cryptech.is
git at cryptech.is
Tue Mar 17 13:14:16 UTC 2015
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paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha1.
commit 6131547a064b1c83d7fadf6edbc57144bd404f0e
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Fri Mar 14 22:24:24 2014 +0100
Updating interface. Addding self resetting control regs. Fixing missing input port declaration that caused errors during simulation in ModelSim.
---
src/rtl/sha1.v | 217 ++++++++++++++++++++++++++++++++++++-------------------
src/tb/tb_sha1.v | 139 +++++++++++++++++++++++++++++------
2 files changed, 257 insertions(+), 99 deletions(-)
diff --git a/src/rtl/sha1.v b/src/rtl/sha1.v
index 9d2775f..6033672 100644
--- a/src/rtl/sha1.v
+++ b/src/rtl/sha1.v
@@ -7,7 +7,8 @@
//
//
// Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
+// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
@@ -43,12 +44,12 @@ module sha1(
// Control.
input wire cs,
- input wire write_read,
+ input wire we,
// Data ports.
input wire [7 : 0] address,
- input wire [31 : 0] data_in,
- output wire [31 : 0] data_out,
+ input wire [31 : 0] write_data,
+ output wire [31 : 0] read_data,
output wire error
);
@@ -99,8 +100,16 @@ module sha1(
// Registers including update variables and write enable.
//----------------------------------------------------------------
reg init_reg;
+ reg init_new;
+ reg init_we;
+ reg init_set;
+ reg init_rst;
+
reg next_reg;
- reg ctrl_we;
+ reg next_new;
+ reg next_we;
+ reg next_set;
+ reg next_rst;
reg ready_reg;
@@ -152,7 +161,7 @@ module sha1(
wire [159 : 0] core_digest;
wire core_digest_valid;
- reg [31 : 0] tmp_data_out;
+ reg [31 : 0] tmp_read_data;
reg tmp_error;
@@ -168,7 +177,7 @@ module sha1(
block8_reg, block9_reg, block10_reg, block11_reg,
block12_reg, block13_reg, block14_reg, block15_reg};
- assign data_out = tmp_data_out;
+ assign read_data = tmp_read_data;
assign error = tmp_error;
@@ -228,10 +237,14 @@ module sha1(
ready_reg <= core_ready;
digest_valid_reg <= core_digest_valid;
- if (ctrl_we)
+ if (init_we)
begin
- init_reg <= data_in[CTRL_INIT_BIT];
- next_reg <= data_in[CTRL_NEXT_BIT];
+ init_reg <= init_new;
+ end
+
+ if (next_we)
+ begin
+ next_reg <= next_new;
end
if (core_digest_valid)
@@ -241,82 +254,82 @@ module sha1(
if (block0_we)
begin
- block0_reg <= data_in;
+ block0_reg <= write_data;
end
if (block1_we)
begin
- block1_reg <= data_in;
+ block1_reg <= write_data;
end
if (block2_we)
begin
- block2_reg <= data_in;
+ block2_reg <= write_data;
end
if (block3_we)
begin
- block3_reg <= data_in;
+ block3_reg <= write_data;
end
if (block4_we)
begin
- block4_reg <= data_in;
+ block4_reg <= write_data;
end
if (block5_we)
begin
- block5_reg <= data_in;
+ block5_reg <= write_data;
end
if (block6_we)
begin
- block6_reg <= data_in;
+ block6_reg <= write_data;
end
if (block7_we)
begin
- block7_reg <= data_in;
+ block7_reg <= write_data;
end
if (block8_we)
begin
- block8_reg <= data_in;
+ block8_reg <= write_data;
end
if (block9_we)
begin
- block9_reg <= data_in;
+ block9_reg <= write_data;
end
if (block10_we)
begin
- block10_reg <= data_in;
+ block10_reg <= write_data;
end
if (block11_we)
begin
- block11_reg <= data_in;
+ block11_reg <= write_data;
end
if (block12_we)
begin
- block12_reg <= data_in;
+ block12_reg <= write_data;
end
if (block13_we)
begin
- block13_reg <= data_in;
+ block13_reg <= write_data;
end
if (block14_we)
begin
- block14_reg <= data_in;
+ block14_reg <= write_data;
end
if (block15_we)
begin
- block15_reg <= data_in;
+ block15_reg <= write_data;
end
end
@@ -324,41 +337,95 @@ module sha1(
//----------------------------------------------------------------
+ // flag_reset
+ //
+ // Logic to reset init and next flags that has been set.
+ //----------------------------------------------------------------
+ always @*
+ begin : flag_reset
+ init_new = 0;
+ init_we = 0;
+ next_new = 0;
+ next_we = 0;
+
+ if (init_set)
+ begin
+ init_new = 1;
+ init_we = 1;
+ end
+ else if (init_reg)
+ begin
+ init_new = 0;
+ init_we = 1;
+ end
+
+ if (next_set)
+ begin
+ next_new = 1;
+ next_we = 1;
+ end
+ else if (next_reg)
+ begin
+ next_new = 0;
+ next_we = 1;
+ end
+ end
+
+ //----------------------------------------------------------------
// api
//
// The interface command decoding logic.
//----------------------------------------------------------------
always @*
begin : api
- ctrl_we = 0;
- block0_we = 0;
- block1_we = 0;
- block2_we = 0;
- block3_we = 0;
- block4_we = 0;
- block5_we = 0;
- block6_we = 0;
- block7_we = 0;
- block8_we = 0;
- block9_we = 0;
- block10_we = 0;
- block11_we = 0;
- block12_we = 0;
- block13_we = 0;
- block14_we = 0;
- block15_we = 0;
- tmp_data_out = 32'h00000000;
- tmp_error = 0;
+ init_set = 0;
+ init_rst = 0;
+ next_set = 0;
+ next_rst = 0;
+ block0_we = 0;
+ block1_we = 0;
+ block2_we = 0;
+ block3_we = 0;
+ block4_we = 0;
+ block5_we = 0;
+ block6_we = 0;
+ block7_we = 0;
+ block8_we = 0;
+ block9_we = 0;
+ block10_we = 0;
+ block11_we = 0;
+ block12_we = 0;
+ block13_we = 0;
+ block14_we = 0;
+ block15_we = 0;
+ tmp_read_data = 32'h00000000;
+ tmp_error = 0;
if (cs)
begin
- if (write_read)
+ if (we)
begin
case (address)
// Write operations.
ADDR_CTRL:
begin
- ctrl_we = 1;
+ if (write_data[CTRL_INIT_BIT])
+ begin
+ init_set = 1;
+ end
+ else
+ begin
+ init_rst = 1;
+ end
+
+ if (write_data[CTRL_NEXT_BIT])
+ begin
+ next_set = 1;
+ end
+ else
+ begin
+ next_rst = 1;
+ end
end
ADDR_BLOCK0:
@@ -445,7 +512,7 @@ module sha1(
begin
tmp_error = 1;
end
- endcase // case (address)
+ endcase // case (addr)
end // if (write_read)
else
@@ -454,139 +521,139 @@ module sha1(
// Read operations.
ADDR_NAME0:
begin
- tmp_data_out = CORE_NAME0;
+ tmp_read_data = CORE_NAME0;
end
ADDR_NAME1:
begin
- tmp_data_out = CORE_NAME1;
+ tmp_read_data = CORE_NAME1;
end
ADDR_VERSION:
begin
- tmp_data_out = CORE_VERSION;
+ tmp_read_data = CORE_VERSION;
end
ADDR_CTRL:
begin
- tmp_data_out = {28'h0000000, 2'b00, next_reg, init_reg};
+ tmp_read_data = {28'h0000000, 2'b00, next_reg, init_reg};
end
ADDR_STATUS:
begin
- tmp_data_out = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
+ tmp_read_data = {28'h0000000, 2'b00, digest_valid_reg, ready_reg};
end
ADDR_BLOCK0:
begin
- tmp_data_out = block0_reg;
+ tmp_read_data = block0_reg;
end
ADDR_BLOCK1:
begin
- tmp_data_out = block1_reg;
+ tmp_read_data = block1_reg;
end
ADDR_BLOCK2:
begin
- tmp_data_out = block2_reg;
+ tmp_read_data = block2_reg;
end
ADDR_BLOCK3:
begin
- tmp_data_out = block3_reg;
+ tmp_read_data = block3_reg;
end
ADDR_BLOCK4:
begin
- tmp_data_out = block4_reg;
+ tmp_read_data = block4_reg;
end
ADDR_BLOCK5:
begin
- tmp_data_out = block5_reg;
+ tmp_read_data = block5_reg;
end
ADDR_BLOCK6:
begin
- tmp_data_out = block6_reg;
+ tmp_read_data = block6_reg;
end
ADDR_BLOCK7:
begin
- tmp_data_out = block7_reg;
+ tmp_read_data = block7_reg;
end
ADDR_BLOCK8:
begin
- tmp_data_out = block8_reg;
+ tmp_read_data = block8_reg;
end
ADDR_BLOCK9:
begin
- tmp_data_out = block9_reg;
+ tmp_read_data = block9_reg;
end
ADDR_BLOCK10:
begin
- tmp_data_out = block10_reg;
+ tmp_read_data = block10_reg;
end
ADDR_BLOCK11:
begin
- tmp_data_out = block11_reg;
+ tmp_read_data = block11_reg;
end
ADDR_BLOCK12:
begin
- tmp_data_out = block12_reg;
+ tmp_read_data = block12_reg;
end
ADDR_BLOCK13:
begin
- tmp_data_out = block13_reg;
+ tmp_read_data = block13_reg;
end
ADDR_BLOCK14:
begin
- tmp_data_out = block14_reg;
+ tmp_read_data = block14_reg;
end
ADDR_BLOCK15:
begin
- tmp_data_out = block15_reg;
+ tmp_read_data = block15_reg;
end
ADDR_DIGEST0:
begin
- tmp_data_out = digest_reg[159 : 128];
+ tmp_read_data = digest_reg[159 : 128];
end
ADDR_DIGEST1:
begin
- tmp_data_out = digest_reg[127 : 96];
+ tmp_read_data = digest_reg[127 : 96];
end
ADDR_DIGEST2:
begin
- tmp_data_out = digest_reg[95 : 64];
+ tmp_read_data = digest_reg[95 : 64];
end
ADDR_DIGEST3:
begin
- tmp_data_out = digest_reg[63 : 32];
+ tmp_read_data = digest_reg[63 : 32];
end
ADDR_DIGEST4:
begin
- tmp_data_out = digest_reg[31 : 0];
+ tmp_read_data = digest_reg[31 : 0];
end
default:
begin
tmp_error = 1;
end
- endcase // case (address)
+ endcase // case (addr)
end
end
end // addr_decoder
diff --git a/src/tb/tb_sha1.v b/src/tb/tb_sha1.v
index 632b4e9..6e39075 100644
--- a/src/tb/tb_sha1.v
+++ b/src/tb/tb_sha1.v
@@ -5,8 +5,8 @@
// Testbench for the SHA-1 top level wrapper.
//
//
-// Author: Joachim Strombergson
-// Copyright (c) 2014 SUNET
+// Copyright (c) 2014, SUNET
+// All rights reserved.
//
// Redistribution and use in source and binary forms, with or
// without modification, are permitted provided that the following
@@ -45,7 +45,8 @@ module tb_sha1();
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter DEBUG = 0;
+ parameter DEBUG_CORE = 0;
+ parameter DEBUG_TOP = 0;
parameter CLK_HALF_PERIOD = 2;
@@ -110,16 +111,17 @@ module tb_sha1();
// Device Under Test.
//----------------------------------------------------------------
sha1 dut(
- .clk(tb_clk),
- .reset_n(tb_reset_n),
+ .clk(tb_clk),
+ .reset_n(tb_reset_n),
- .cs(tb_cs),
- .write_read(tb_write_read),
+ .cs(tb_cs),
+ .we(tb_write_read),
- .address(tb_address),
- .data_in(tb_data_in),
- .data_out(tb_data_out)
- );
+ .address(tb_address),
+ .write_data(tb_data_in),
+ .read_data(tb_data_out),
+ .error(tb_error)
+ );
//----------------------------------------------------------------
@@ -138,20 +140,108 @@ module tb_sha1();
//----------------------------------------------------------------
always
begin : sys_monitor
+ if (DEBUG_CORE)
+ begin
+ dump_core_state();
+ end
+
+ if (DEBUG_TOP)
+ begin
+ dump_top_state();
+ end
+
#(2 * CLK_HALF_PERIOD);
cycle_ctr = cycle_ctr + 1;
end
//----------------------------------------------------------------
- // dump_dut_state()
+ // dump_top_state()
+ //
+ // Dump state of the the top of the dut.
+ //----------------------------------------------------------------
+ task dump_top_state();
+ begin
+ $display("State of top");
+ $display("-------------");
+ $display("Inputs and outputs:");
+ $display("cs = 0x%01x, we = 0x%01x", dut.cs, dut.we);
+ $display("address = 0x%02x, write_data = 0x%08x", dut.address, dut.write_data);
+ $display("error = 0x%01x, read_data = 0x%08x", dut.error, dut.read_data);
+ $display("");
+
+ $display("Control and status flags:");
+ $display("init = 0x%01x, next = 0x%01x, ready = 0x%01x",
+ dut.init_reg, dut.next_reg, dut.ready_reg);
+ $display("");
+
+ $display("block registers:");
+ $display("block0_reg = 0x%08x, block1_reg = 0x%08x, block2_reg = 0x%08x, block3_reg = 0x%08x",
+ dut.block0_reg, dut.block1_reg, dut.block2_reg, dut.block3_reg);
+
+ $display("block4_reg = 0x%08x, block5_reg = 0x%08x, block6_reg = 0x%08x, block7_reg = 0x%08x",
+ dut.block4_reg, dut.block5_reg, dut.block6_reg, dut.block7_reg);
+
+ $display("block8_reg = 0x%08x, block9_reg = 0x%08x, block10_reg = 0x%08x, block11_reg = 0x%08x",
+ dut.block8_reg, dut.block9_reg, dut.block10_reg, dut.block11_reg);
+
+ $display("block12_reg = 0x%08x, block13_reg = 0x%08x, block14_reg = 0x%08x, block15_reg = 0x%08x",
+ dut.block12_reg, dut.block13_reg, dut.block14_reg, dut.block15_reg);
+ $display("");
+
+ $display("Digest registers:");
+ $display("digest_reg = 0x%040x", dut.digest_reg);
+ $display("");
+ end
+ endtask // dump_top_state
+
+
+ //----------------------------------------------------------------
+ // dump_core_state()
//
- // Dump the state of the dump when needed.
+ // Dump the state of the core inside the dut.
//----------------------------------------------------------------
- task dump_dut_state();
+ task dump_core_state();
begin
+ $display("State of core");
+ $display("-------------");
+ $display("Inputs and outputs:");
+ $display("init = 0x%01x, next = 0x%01x",
+ dut.core.init, dut.core.next);
+ $display("block = 0x%0128x", dut.core.block);
+
+ $display("ready = 0x%01x, valid = 0x%01x",
+ dut.core.ready, dut.core.digest_valid);
+ $display("digest = 0x%040x", dut.core.digest);
+ $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x, H4_reg = 0x%08x",
+ dut.core.H0_reg, dut.core.H1_reg, dut.core.H2_reg, dut.core.H3_reg, dut.core.H4_reg);
+ $display("");
+
+ $display("Control signals and counter:");
+ $display("sha1_ctrl_reg = 0x%01x", dut.core.sha1_ctrl_reg);
+ $display("digest_init = 0x%01x, digest_update = 0x%01x",
+ dut.core.digest_init, dut.core.digest_update);
+ $display("state_init = 0x%01x, state_update = 0x%01x",
+ dut.core.state_init, dut.core.state_update);
+ $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
+ dut.core.first_block, dut.core.ready_flag, dut.core.w_init);
+ $display("round_ctr_inc = 0x%01x, round_ctr_rst = 0x%01x, round_ctr_reg = 0x%02x",
+ dut.core.round_ctr_inc, dut.core.round_ctr_rst, dut.core.round_ctr_reg);
+ $display("");
+
+ $display("State registers:");
+ $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x, e_reg = 0x%08x",
+ dut.core.a_reg, dut.core.b_reg, dut.core.c_reg, dut.core.d_reg, dut.core.e_reg);
+ $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x, e_new = 0x%08x",
+ dut.core.a_new, dut.core.b_new, dut.core.c_new, dut.core.d_new, dut.core.e_new);
+ $display("");
+
+ $display("State update values:");
+ $display("f = 0x%08x, k = 0x%08x, t = 0x%08x, w = 0x%08x,",
+ dut.core.state_logic.f, dut.core.state_logic.k, dut.core.state_logic.t, dut.core.w);
+ $display("");
end
- endtask // dump_dut_state
+ endtask // dump_core_state
//----------------------------------------------------------------
@@ -238,7 +328,7 @@ module tb_sha1();
// the word read will be available in the global variable
// read_data.
//----------------------------------------------------------------
- task read_word(input [7 : 0] address);
+ task read_word(input [7 : 0] address);
begin
tb_address = address;
tb_cs = 1;
@@ -247,7 +337,7 @@ module tb_sha1();
read_data = tb_data_out;
tb_cs = 0;
- if (DEBUG)
+ if (DEBUG_TOP)
begin
$display("*** Reading 0x%08x from 0x%02x.", read_data, address);
$display("");
@@ -264,7 +354,7 @@ module tb_sha1();
task write_word(input [7 : 0] address,
input [31 : 0] word);
begin
- if (DEBUG)
+ if (DEBUG_TOP)
begin
$display("*** Writing 0x%08x to 0x%02x.", word, address);
$display("");
@@ -363,8 +453,9 @@ module tb_sha1();
//
// Perform test of a single block digest.
//----------------------------------------------------------------
- task single_block_test([511 : 0] block,
- [159 : 0] expected);
+ task single_block_test(input [511 : 0] block,
+ input [159 : 0] expected
+ );
begin
$display("*** TC%01d - Single block test started.", tc_ctr);
@@ -398,10 +489,10 @@ module tb_sha1();
// Perform test of a double block digest. Note that we check
// the digests for both the first and final block.
//----------------------------------------------------------------
- task double_block_test([511 : 0] block0,
- [159 : 0] expected0,
- [511 : 0] block1,
- [159 : 0] expected1
+ task double_block_test(input [511 : 0] block0,
+ input [159 : 0] expected0,
+ input [511 : 0] block1,
+ input [159 : 0] expected1
);
begin
$display("*** TC%01d - Double block test started.", tc_ctr);
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