[Cryptech-Commits] [staging/core/hash/sha512] 07/09: Fixes of nits in #8 found with the verilator linter.
git at cryptech.is
git at cryptech.is
Tue Mar 17 13:15:19 UTC 2015
This is an automated email from the git hooks/post-receive script.
paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha512.
commit 884e61e8e11fa99401b39654e13f94b4a1c8ae53
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Thu Nov 6 13:34:48 2014 +0100
Fixes of nits in #8 found with the verilator linter.
---
src/rtl/sha512_core.v | 195 ++++++++++++++++++++++++------------------------
src/rtl/sha512_w_mem.v | 104 +++++++++++++-------------
src/tb/tb_sha512_core.v | 176 ++++++++++++++++++++++---------------------
3 files changed, 238 insertions(+), 237 deletions(-)
diff --git a/src/rtl/sha512_core.v b/src/rtl/sha512_core.v
index 73bbcee..44af0b1 100644
--- a/src/rtl/sha512_core.v
+++ b/src/rtl/sha512_core.v
@@ -9,30 +9,30 @@
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -40,29 +40,29 @@
module sha512_core(
input wire clk,
input wire reset_n,
-
+
input wire init,
input wire next,
input wire [1 : 0] mode,
-
+
input wire [1023 : 0] block,
-
+
output wire ready,
output wire [511 : 0] digest,
output wire digest_valid
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter SHA512_ROUNDS = 79;
-
+
parameter CTRL_IDLE = 0;
parameter CTRL_ROUNDS = 1;
parameter CTRL_DONE = 2;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -101,7 +101,7 @@ module sha512_core(
reg [63 : 0] H7_reg;
reg [63 : 0] H7_new;
reg H_we;
-
+
reg [6 : 0] t_ctr_reg;
reg [6 : 0] t_ctr_new;
reg t_ctr_we;
@@ -111,12 +111,12 @@ module sha512_core(
reg digest_valid_reg;
reg digest_valid_new;
reg digest_valid_we;
-
+
reg [1 : 0] sha512_ctrl_reg;
reg [1 : 0] sha512_ctrl_new;
reg sha512_ctrl_we;
-
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
@@ -138,7 +138,7 @@ module sha512_core(
reg w_init;
reg w_next;
wire [63 : 0] w_data;
-
+
wire [63 : 0] H0_0;
wire [63 : 0] H0_1;
wire [63 : 0] H0_2;
@@ -148,53 +148,53 @@ module sha512_core(
wire [63 : 0] H0_6;
wire [63 : 0] H0_7;
-
+
//----------------------------------------------------------------
// Module instantiantions.
//----------------------------------------------------------------
- sha512_k_constants k_constants(
- .addr(t_ctr_reg),
- .K(k_data)
- );
-
-
- sha512_h_constants h_constants(
- .mode(mode),
-
- .H0(H0_0),
- .H1(H0_1),
- .H2(H0_2),
- .H3(H0_3),
- .H4(H0_4),
- .H5(H0_5),
- .H6(H0_6),
- .H7(H0_7)
- );
-
-
- sha512_w_mem w_mem(
- .clk(clk),
- .reset_n(reset_n),
-
- .block(block),
-
- .init(w_init),
- .next(w_next),
- .w(w_data)
- );
-
-
+ sha512_k_constants k_constants_inst(
+ .addr(t_ctr_reg),
+ .K(k_data)
+ );
+
+
+ sha512_h_constants h_constants_inst(
+ .mode(mode),
+
+ .H0(H0_0),
+ .H1(H0_1),
+ .H2(H0_2),
+ .H3(H0_3),
+ .H4(H0_4),
+ .H5(H0_5),
+ .H6(H0_6),
+ .H7(H0_7)
+ );
+
+
+ sha512_w_mem w_mem_inst(
+ .clk(clk),
+ .reset_n(reset_n),
+
+ .block(block),
+
+ .init(w_init),
+ .next(w_next),
+ .w(w_data)
+ );
+
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign ready = ready_flag;
-
+
assign digest = {H0_reg, H1_reg, H2_reg, H3_reg,
H4_reg, H5_reg, H6_reg, H7_reg};
-
+
assign digest_valid = digest_valid_reg;
-
-
+
+
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
@@ -227,7 +227,7 @@ module sha512_core(
end
else
begin
-
+
if (a_h_we)
begin
a_reg <= a_new;
@@ -251,7 +251,7 @@ module sha512_core(
H6_reg <= H6_new;
H7_reg <= H7_new;
end
-
+
if (t_ctr_we)
begin
t_ctr_reg <= t_ctr_new;
@@ -261,7 +261,7 @@ module sha512_core(
begin
digest_valid_reg <= digest_valid_new;
end
-
+
if (sha512_ctrl_we)
begin
sha512_ctrl_reg <= sha512_ctrl_new;
@@ -269,7 +269,7 @@ module sha512_core(
end
end // reg_update
-
+
//----------------------------------------------------------------
// digest_logic
//
@@ -325,12 +325,12 @@ module sha512_core(
reg [63 : 0] sum1;
reg [63 : 0] ch;
- sum1 = {e_reg[13 : 0], e_reg[63 : 14]} ^
- {e_reg[17 : 0], e_reg[63 : 18]} ^
+ sum1 = {e_reg[13 : 0], e_reg[63 : 14]} ^
+ {e_reg[17 : 0], e_reg[63 : 18]} ^
{e_reg[40 : 0], e_reg[63 : 41]};
ch = (e_reg & f_reg) ^ ((~e_reg) & g_reg);
-
+
t1 = h_reg + sum1 + ch + k_data + w_data;
end // t1_logic
@@ -350,11 +350,11 @@ module sha512_core(
{a_reg[38 : 0], a_reg[63 : 39]};
maj = (a_reg & b_reg) ^ (a_reg & c_reg) ^ (b_reg & c_reg);
-
+
t2 = sum0 + maj;
end // t2_logic
-
-
+
+
//----------------------------------------------------------------
// state_logic
//
@@ -363,9 +363,6 @@ module sha512_core(
//----------------------------------------------------------------
always @*
begin : state_logic
- reg [63 : 0] tmp1;
- reg [63 : 0] tmp2;
-
a_new = 64'h00000000;
b_new = 64'h00000000;
c_new = 64'h00000000;
@@ -375,7 +372,7 @@ module sha512_core(
g_new = 64'h00000000;
h_new = 64'h00000000;
a_h_we = 0;
-
+
if (state_init)
begin
if (first_block)
@@ -403,7 +400,7 @@ module sha512_core(
a_h_we = 1;
end
end
-
+
if (state_update)
begin
a_new = t1 + t2;
@@ -418,18 +415,18 @@ module sha512_core(
end
end // state_logic
-
+
//----------------------------------------------------------------
// t_ctr
//
- // Update logic for the round counter, a monotonically
+ // Update logic for the round counter, a monotonically
// increasing counter with reset.
//----------------------------------------------------------------
always @*
begin : t_ctr
t_ctr_new = 7'h00;
t_ctr_we = 0;
-
+
if (t_ctr_rst)
begin
t_ctr_new = 7'h00;
@@ -443,7 +440,7 @@ module sha512_core(
end
end // t_ctr
-
+
//----------------------------------------------------------------
// sha512_ctrl_fsm
//
@@ -456,28 +453,28 @@ module sha512_core(
state_init = 0;
state_update = 0;
-
+
first_block = 0;
ready_flag = 0;
w_init = 0;
w_next = 0;
-
+
t_ctr_inc = 0;
t_ctr_rst = 0;
-
+
digest_valid_new = 0;
digest_valid_we = 0;
-
+
sha512_ctrl_new = CTRL_IDLE;
sha512_ctrl_we = 0;
-
+
case (sha512_ctrl_reg)
CTRL_IDLE:
begin
ready_flag = 1;
-
+
if (init)
begin
digest_init = 1;
@@ -503,7 +500,7 @@ module sha512_core(
end
end
-
+
CTRL_ROUNDS:
begin
w_next = 1;
@@ -517,7 +514,7 @@ module sha512_core(
end
end
-
+
CTRL_DONE:
begin
digest_update = 1;
@@ -529,7 +526,7 @@ module sha512_core(
end
endcase // case (sha512_ctrl_reg)
end // sha512_ctrl_fsm
-
+
endmodule // sha512_core
//======================================================================
diff --git a/src/rtl/sha512_w_mem.v b/src/rtl/sha512_w_mem.v
index 47113b9..824316d 100644
--- a/src/rtl/sha512_w_mem.v
+++ b/src/rtl/sha512_w_mem.v
@@ -2,37 +2,37 @@
//
// sha512_w_mem_regs.v
// -------------------
-// The W memory for the SHA-512 core. This version uses 16
+// The W memory for the SHA-512 core. This version uses 16
// 32-bit registers as a sliding window to generate the 64 words.
//
//
// Author: Joachim Strombergson
// Copyright (c) 2014 Secworks Sweden AB
// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -48,14 +48,14 @@ module sha512_w_mem(
output wire [63 : 0] w
);
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
parameter CTRL_IDLE = 1'b0;
parameter CTRL_UPDATE = 1'b1;
-
-
+
+
//----------------------------------------------------------------
// Registers including update variables and write enable.
//----------------------------------------------------------------
@@ -77,31 +77,31 @@ module sha512_w_mem(
reg [63 : 0] w_mem14_new;
reg [63 : 0] w_mem15_new;
reg w_mem_we;
-
+
reg [6 : 0] w_ctr_reg;
reg [6 : 0] w_ctr_new;
reg w_ctr_we;
reg w_ctr_inc;
reg w_ctr_rst;
-
+
reg sha512_w_mem_ctrl_reg;
reg sha512_w_mem_ctrl_new;
reg sha512_w_mem_ctrl_we;
-
-
+
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
reg [63 : 0] w_tmp;
reg [63 : 0] w_new;
-
-
+
+
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
assign w = w_tmp;
-
-
+
+
//----------------------------------------------------------------
// reg_update
// Update functionality for all registers in the core.
@@ -152,12 +152,12 @@ module sha512_w_mem(
w_mem[14] <= w_mem14_new;
w_mem[15] <= w_mem15_new;
end
-
+
if (w_ctr_we)
begin
w_ctr_reg <= w_ctr_new;
end
-
+
if (sha512_w_mem_ctrl_we)
begin
sha512_w_mem_ctrl_reg <= sha512_w_mem_ctrl_new;
@@ -165,7 +165,7 @@ module sha512_w_mem(
end
end // reg_update
-
+
//----------------------------------------------------------------
// select_w
//
@@ -183,7 +183,7 @@ module sha512_w_mem(
w_tmp = w_new;
end
end // select_w
-
+
//----------------------------------------------------------------
// w_new_logic
@@ -217,7 +217,7 @@ module sha512_w_mem(
w_mem14_new = 64'h0000000000000000;
w_mem15_new = 64'h0000000000000000;
w_mem_we = 0;
-
+
w_0 = w_mem[0];
w_1 = w_mem[1];
w_9 = w_mem[9];
@@ -226,13 +226,13 @@ module sha512_w_mem(
d0 = {w_1[0], w_1[63 : 1]} ^ // ROTR1
{w_1[7 : 0], w_1[63 : 8]} ^ // ROTR8
{7'b0000000, w_1[63 : 7]}; // SHR7
-
+
d1 = {w_14[18 : 0], w_14[63 : 19]} ^ // ROTR19
{w_14[60 : 0], w_14[63 : 61]} ^ // ROTR61
{6'b000000, w_14[63 : 6]}; // SHR6
-
+
w_new = w_0 + d0 + w_9 + d1;
-
+
if (init)
begin
w_mem00_new = block[1023 : 960];
@@ -274,8 +274,8 @@ module sha512_w_mem(
w_mem_we = 1;
end
end // w_mem_update_logic
-
-
+
+
//----------------------------------------------------------------
// w_ctr
// W schedule adress counter. Counts from 0x10 to 0x3f and
@@ -285,7 +285,7 @@ module sha512_w_mem(
begin : w_ctr
w_ctr_new = 0;
w_ctr_we = 0;
-
+
if (w_ctr_rst)
begin
w_ctr_new = 7'h00;
@@ -299,7 +299,7 @@ module sha512_w_mem(
end
end // w_ctr
-
+
//----------------------------------------------------------------
// sha512_w_mem_fsm
// Logic for the w shedule FSM.
@@ -308,10 +308,10 @@ module sha512_w_mem(
begin : sha512_w_mem_fsm
w_ctr_rst = 0;
w_ctr_inc = 0;
-
+
sha512_w_mem_ctrl_new = CTRL_IDLE;
sha512_w_mem_ctrl_we = 0;
-
+
case (sha512_w_mem_ctrl_reg)
CTRL_IDLE:
begin
@@ -322,15 +322,15 @@ module sha512_w_mem(
sha512_w_mem_ctrl_we = 1;
end
end
-
+
CTRL_UPDATE:
begin
if (next)
begin
w_ctr_inc = 1;
end
-
- if (w_ctr_reg == 6'h3f)
+
+ if (w_ctr_reg == 7'h3f)
begin
sha512_w_mem_ctrl_new = CTRL_IDLE;
sha512_w_mem_ctrl_we = 1;
diff --git a/src/tb/tb_sha512_core.v b/src/tb/tb_sha512_core.v
index d0e05f7..e4d3bb8 100644
--- a/src/tb/tb_sha512_core.v
+++ b/src/tb/tb_sha512_core.v
@@ -8,30 +8,30 @@
// Author: Joachim Strombergson
// Copyright (c) 2014, SUNET
// All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or
-// without modification, are permitted provided that the following
-// conditions are met:
-//
-// 1. Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// 2. Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in
-// the documentation and/or other materials provided with the
-// distribution.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
-// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
-// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
-// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
-// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
-// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+//
+// Redistribution and use in source and binary forms, with or
+// without modification, are permitted provided that the following
+// conditions are met:
+//
+// 1. Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// 2. Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in
+// the documentation and/or other materials provided with the
+// distribution.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+// FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+// COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
// BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
-// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
+// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+// STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
// ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
//
//======================================================================
@@ -46,7 +46,7 @@
// Test module.
//------------------------------------------------------------------
module tb_sha512_core();
-
+
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
@@ -59,8 +59,8 @@ module tb_sha512_core();
parameter MODE_SHA_512_256 = 1;
parameter MODE_SHA_384 = 2;
parameter MODE_SHA_512 = 3;
-
-
+
+
//----------------------------------------------------------------
// Register and Wire declarations.
//----------------------------------------------------------------
@@ -77,39 +77,39 @@ module tb_sha512_core();
wire tb_ready;
wire [511 : 0] tb_digest;
wire tb_digest_valid;
-
-
+
+
//----------------------------------------------------------------
// Device Under Test.
//----------------------------------------------------------------
sha512_core dut(
.clk(tb_clk),
.reset_n(tb_reset_n),
-
+
.init(tb_init),
.next(tb_next),
.mode(tb_mode),
.block(tb_block),
-
+
.ready(tb_ready),
-
+
.digest(tb_digest),
.digest_valid(tb_digest_valid)
);
-
+
//----------------------------------------------------------------
// clk_gen
//
// Always running clock generator process.
//----------------------------------------------------------------
- always
+ always
begin : clk_gen
#CLK_HALF_PERIOD;
tb_clk = !tb_clk;
end // clk_gen
-
+
//----------------------------------------------------------------
// sys_monitor()
@@ -127,7 +127,7 @@ module tb_sha512_core();
end
end
-
+
//----------------------------------------------------------------
// dump_dut_state()
//
@@ -138,40 +138,40 @@ module tb_sha512_core();
$display("State of DUT");
$display("------------");
$display("Inputs and outputs:");
- $display("init = 0x%01x, next = 0x%01x. mode = 0x%01x",
+ $display("init = 0x%01x, next = 0x%01x. mode = 0x%01x",
dut.init, dut.next, dut.mode);
$display("block = 0x%0128x", dut.block);
- $display("ready = 0x%01x, valid = 0x%01x",
+ $display("ready = 0x%01x, valid = 0x%01x",
dut.ready, dut.digest_valid);
$display("digest = 0x%064x", dut.digest);
- $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
+ $display("H0_reg = 0x%08x, H1_reg = 0x%08x, H2_reg = 0x%08x, H3_reg = 0x%08x",
dut.H0_reg, dut.H1_reg, dut.H2_reg, dut.H3_reg);
- $display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
+ $display("H4_reg = 0x%08x, H5_reg = 0x%08x, H6_reg = 0x%08x, H7_reg = 0x%08x",
dut.H4_reg, dut.H5_reg, dut.H6_reg, dut.H7_reg);
$display("");
-
+
$display("Control signals and counter:");
$display("sha512_ctrl_reg = 0x%02x", dut.sha512_ctrl_reg);
- $display("digest_init = 0x%01x, digest_update = 0x%01x",
+ $display("digest_init = 0x%01x, digest_update = 0x%01x",
dut.digest_init, dut.digest_update);
- $display("state_init = 0x%01x, state_update = 0x%01x",
+ $display("state_init = 0x%01x, state_update = 0x%01x",
dut.state_init, dut.state_update);
- $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
+ $display("first_block = 0x%01x, ready_flag = 0x%01x, w_init = 0x%01x",
dut.first_block, dut.ready_flag, dut.w_init);
- $display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
+ $display("t_ctr_inc = 0x%01x, t_ctr_rst = 0x%01x, t_ctr_reg = 0x%02x",
dut.t_ctr_inc, dut.t_ctr_rst, dut.t_ctr_reg);
$display("");
$display("State registers:");
- $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
+ $display("a_reg = 0x%08x, b_reg = 0x%08x, c_reg = 0x%08x, d_reg = 0x%08x",
dut.a_reg, dut.b_reg, dut.c_reg, dut.d_reg);
- $display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
+ $display("e_reg = 0x%08x, f_reg = 0x%08x, g_reg = 0x%08x, h_reg = 0x%08x",
dut.e_reg, dut.f_reg, dut.g_reg, dut.h_reg);
$display("");
- $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
+ $display("a_new = 0x%08x, b_new = 0x%08x, c_new = 0x%08x, d_new = 0x%08x",
dut.a_new, dut.b_new, dut.c_new, dut.d_new);
- $display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
+ $display("e_new = 0x%08x, f_new = 0x%08x, g_new = 0x%08x, h_new = 0x%08x",
dut.e_new, dut.f_new, dut.g_new, dut.h_new);
$display("");
@@ -182,7 +182,7 @@ module tb_sha512_core();
end
endtask // dump_dut_state
-
+
//----------------------------------------------------------------
// dump_dut_wmem()
//
@@ -192,19 +192,23 @@ module tb_sha512_core();
begin
$display("State of DUT WMEM");
$display("-----------------");
- $display("W[00] = 0x%016x, W[01] = 0x%016x, W[02] = 0x%016x, W[03] = 0x%016x",
- dut.w_mem.w_mem[00], dut.w_mem.w_mem[01], dut.w_mem.w_mem[02], dut.w_mem.w_mem[03]);
- $display("W[04] = 0x%016x, W[05] = 0x%016x, W[06] = 0x%016x, W[07] = 0x%016x",
- dut.w_mem.w_mem[04], dut.w_mem.w_mem[05], dut.w_mem.w_mem[06], dut.w_mem.w_mem[07]);
- $display("W[08] = 0x%016x, W[09] = 0x%016x, W[10] = 0x%016x, W[11] = 0x%016x",
- dut.w_mem.w_mem[08], dut.w_mem.w_mem[09], dut.w_mem.w_mem[10], dut.w_mem.w_mem[11]);
- $display("W[12] = 0x%016x, W[13] = 0x%016x, W[14] = 0x%016x, W[15] = 0x%016x",
- dut.w_mem.w_mem[12], dut.w_mem.w_mem[13], dut.w_mem.w_mem[14], dut.w_mem.w_mem[15]);
+ $display("W[00] = 0x%016x, W[01] = 0x%016x, W[02] = 0x%016x, W[03] = 0x%016x",
+ dut.w_mem_inst.w_mem[00], dut.w_mem_inst.w_mem[01],
+ dut.w_mem_inst.w_mem[02], dut.w_mem_inst.w_mem[03]);
+ $display("W[04] = 0x%016x, W[05] = 0x%016x, W[06] = 0x%016x, W[07] = 0x%016x",
+ dut.w_mem_inst.w_mem[04], dut.w_mem_inst.w_mem[05],
+ dut.w_mem_inst.w_mem[06], dut.w_mem_inst.w_mem[07]);
+ $display("W[08] = 0x%016x, W[09] = 0x%016x, W[10] = 0x%016x, W[11] = 0x%016x",
+ dut.w_mem_inst.w_mem[08], dut.w_mem_inst.w_mem[09],
+ dut.w_mem_inst.w_mem[10], dut.w_mem_inst.w_mem[11]);
+ $display("W[12] = 0x%016x, W[13] = 0x%016x, W[14] = 0x%016x, W[15] = 0x%016x",
+ dut.w_mem_inst.w_mem[12], dut.w_mem_inst.w_mem[13],
+ dut.w_mem_inst.w_mem[14], dut.w_mem_inst.w_mem[15]);
$display("");
end
endtask // dump_dut_wmem
-
+
//----------------------------------------------------------------
// reset_dut()
//
@@ -219,7 +223,7 @@ module tb_sha512_core();
end
endtask // reset_dut
-
+
//----------------------------------------------------------------
// init_sim()
//
@@ -231,7 +235,7 @@ module tb_sha512_core();
cycle_ctr = 0;
error_ctr = 0;
tc_ctr = 0;
-
+
tb_clk = 0;
tb_reset_n = 1;
@@ -243,7 +247,7 @@ module tb_sha512_core();
end
endtask // init_dut
-
+
//----------------------------------------------------------------
// display_test_result()
//
@@ -261,7 +265,7 @@ module tb_sha512_core();
end
end
endtask // display_test_result
-
+
//----------------------------------------------------------------
// wait_ready()
@@ -281,7 +285,7 @@ module tb_sha512_core();
end
endtask // wait_ready
-
+
//----------------------------------------------------------------
// single_block_test()
//
@@ -296,13 +300,13 @@ module tb_sha512_core();
begin
$display("*** TC %0d single block test case started.", tc_number);
tc_ctr = tc_ctr + 1;
-
+
tb_block = block;
tb_mode = mode;
tb_init = 1;
#(2 * CLK_PERIOD);
tb_init = 0;
-
+
wait_ready();
case (mode)
@@ -310,41 +314,41 @@ module tb_sha512_core();
begin
mask = {{7{32'hffffffff}}, {9{32'h00000000}}};
end
-
+
MODE_SHA_512_256:
begin
mask = {{8{32'hffffffff}}, {8{32'h00000000}}};
end
-
+
MODE_SHA_384:
begin
mask = {{12{32'hffffffff}}, {4{32'h00000000}}};
end
-
+
MODE_SHA_512:
begin
mask = {16{32'hffffffff}};
end
endcase // case (mode)
-
+
if ((tb_digest & mask) == expected)
begin
$display("*** TC %0d successful.", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d NOT successful.", tc_number);
$display("Expected: 0x%064x", expected);
$display("Got: 0x%064x", tb_digest);
$display("");
-
+
error_ctr = error_ctr + 1;
end
end
endtask // single_block_test
-
+
//----------------------------------------------------------------
// double_block_test()
//
@@ -375,7 +379,7 @@ module tb_sha512_core();
wait_ready();
db_digest1 = tb_digest;
$display("*** TC %0d first block done.", tc_number);
-
+
$display("*** TC %0d second block started.", tc_number);
tb_block = block2;
tb_next = 1;
@@ -383,12 +387,12 @@ module tb_sha512_core();
tb_next = 0;
wait_ready();
$display("*** TC %0d second block done.", tc_number);
-
+
if (db_digest1 == expected1)
begin
$display("*** TC %0d first block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d first block NOT successful", tc_number);
@@ -403,17 +407,17 @@ module tb_sha512_core();
begin
mask = {{7{32'hffffffff}}, {9{32'h00000000}}};
end
-
+
MODE_SHA_512_256:
begin
mask = {{8{32'hffffffff}}, {8{32'h00000000}}};
end
-
+
MODE_SHA_384:
begin
mask = {{12{32'hffffffff}}, {4{32'h00000000}}};
end
-
+
MODE_SHA_512:
begin
mask = {16{32'hffffffff}};
@@ -424,7 +428,7 @@ module tb_sha512_core();
begin
$display("*** TC %0d second block successful", tc_number);
$display("");
- end
+ end
else
begin
$display("*** ERROR: TC %0d second block NOT successful", tc_number);
@@ -440,11 +444,11 @@ module tb_sha512_core();
end
end
endtask // double_block_test
-
-
+
+
//----------------------------------------------------------------
// sha512_core_test
- // The main test functionality.
+ // The main test functionality.
//
// Test cases taken from:
// http://csrc.nist.gov/groups/ST/toolkit/documents/Examples/SHA_All.pdf
@@ -456,7 +460,7 @@ module tb_sha512_core();
reg [511 : 0] tc2_expected;
reg [511 : 0] tc3_expected;
reg [511 : 0] tc4_expected;
-
+
reg [1024 : 0] double_block_one;
reg [1024 : 0] double_block_two;
reg [511 : 0] tc5_expected;
@@ -467,7 +471,7 @@ module tb_sha512_core();
reg [511 : 0] tc10_expected;
reg [511 : 0] tc11_expected;
reg [511 : 0] tc12_expected;
-
+
$display(" -- Testbench for sha512 core started --");
init_sim();
@@ -481,7 +485,7 @@ module tb_sha512_core();
// SHA-512 single block digest and test.
tc1_expected = 512'hDDAF35A193617ABACC417349AE20413112E6FA4E89A97EA20A9EEEE64B55D39A2192992A274FC1A836BA3C23A3FEEBBD454D4423643CE80E2A9AC94FA54CA49F;
single_block_test(8'h01, MODE_SHA_512, single_block, tc1_expected);
-
+
// SHA-512_224 single block digest and test.
tc2_expected = {224'h4634270F707B6A54DAAE7530460842E20E37ED265CEEE9A43E8924AA, {9{32'h00000000}}};
single_block_test(8'h02, MODE_SHA_512_224, single_block, tc2_expected);
@@ -519,7 +523,7 @@ module tb_sha512_core();
tc12_expected = {384'h09330C33F71147E83D192FC782CD1B4753111B173B3B05D22FA08086E3B0F712FCC7C71A557E2DB966C3E9FA91746039, {4{32'h00000000}}};
double_block_test(8'h08, MODE_SHA_384, double_block_one, double_block_two, tc11_expected, tc12_expected);
-
+
display_test_result();
$display("*** Simulation done.");
$finish;
More information about the Commits
mailing list