[Cryptech-Commits] [core/rng/trng] 01/01: Minor cleanup: Changed to localparam for internal parameters. Merged reg update processes to one. Changed name of api read data hold reg and added better update vector name for it.
git at cryptech.is
git at cryptech.is
Thu Mar 26 14:27:47 UTC 2015
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joachim at secworks.se pushed a commit to branch master
in repository core/rng/trng.
commit 7c6b8abc0d5f20c1142b6e7aa7dbdb05940ce786
Author: Joachim Strömbergson <joachim at secworks.se>
Date: Thu Mar 26 15:27:42 2015 +0100
Minor cleanup: Changed to localparam for internal parameters. Merged reg update processes to one. Changed name of api read data hold reg and added better update vector name for it.
---
src/rtl/trng_csprng.v | 121 ++++++++++++++++++++------------------------------
1 file changed, 49 insertions(+), 72 deletions(-)
diff --git a/src/rtl/trng_csprng.v b/src/rtl/trng_csprng.v
index 0797208..79f7afa 100644
--- a/src/rtl/trng_csprng.v
+++ b/src/rtl/trng_csprng.v
@@ -65,35 +65,35 @@ module trng_csprng(
//----------------------------------------------------------------
// Internal constant and parameter definitions.
//----------------------------------------------------------------
- parameter ADDR_CTRL = 8'h10;
- parameter CTRL_ENABLE_BIT = 0;
- parameter CTRL_SEED_BIT = 1;
+ localparam ADDR_CTRL = 8'h10;
+ localparam CTRL_ENABLE_BIT = 0;
+ localparam CTRL_SEED_BIT = 1;
- parameter ADDR_STATUS = 8'h11;
- parameter STATUS_RND_VALID_BIT = 0;
+ localparam ADDR_STATUS = 8'h11;
+ localparam STATUS_RND_VALID_BIT = 0;
- parameter ADDR_RND_DATA = 8'h20;
+ localparam ADDR_RND_DATA = 8'h20;
- parameter ADDR_NUM_ROUNDS = 8'h40;
- parameter ADDR_NUM_BLOCKS_LOW = 8'h41;
- parameter ADDR_NUM_BLOCKS_HIGH = 8'h42;
+ localparam ADDR_NUM_ROUNDS = 8'h40;
+ localparam ADDR_NUM_BLOCKS_LOW = 8'h41;
+ localparam ADDR_NUM_BLOCKS_HIGH = 8'h42;
- parameter CIPHER_KEYLEN256 = 1'b1; // 256 bit key.
- parameter CIPHER_MAX_BLOCKS = 64'h1000000000000000;
+ localparam CIPHER_KEYLEN256 = 1'b1; // 256 bit key.
+ localparam CIPHER_MAX_BLOCKS = 64'h1000000000000000;
- parameter CTRL_IDLE = 4'h0;
- parameter CTRL_SEED0 = 4'h1;
- parameter CTRL_NSYN = 4'h2;
- parameter CTRL_SEED1 = 4'h3;
- parameter CTRL_INIT0 = 4'h4;
- parameter CTRL_INIT1 = 4'h5;
- parameter CTRL_NEXT0 = 4'h6;
- parameter CTRL_NEXT1 = 4'h7;
- parameter CTRL_MORE = 4'h8;
- parameter CTRL_CANCEL = 4'hf;
+ localparam CTRL_IDLE = 4'h0;
+ localparam CTRL_SEED0 = 4'h1;
+ localparam CTRL_NSYN = 4'h2;
+ localparam CTRL_SEED1 = 4'h3;
+ localparam CTRL_INIT0 = 4'h4;
+ localparam CTRL_INIT1 = 4'h5;
+ localparam CTRL_NEXT0 = 4'h6;
+ localparam CTRL_NEXT1 = 4'h7;
+ localparam CTRL_MORE = 4'h8;
+ localparam CTRL_CANCE = 4'hf;
- parameter DEFAULT_NUM_ROUNDS = 5'h18;
- parameter DEFAULT_NUM_BLOCKS = 64'h1000000000000000;
+ localparam DEFAULT_NUM_ROUNDS = 5'h18;
+ localparam DEFAULT_NUM_BLOCKS = 64'h1000000000000000;
//----------------------------------------------------------------
@@ -155,12 +155,13 @@ module trng_csprng(
reg [3 : 0] csprng_ctrl_new;
reg csprng_ctrl_we;
+ reg [31 : 0] read_data_new;
+ reg [31 : 0] read_data_reg;
+
//----------------------------------------------------------------
// Wires.
//----------------------------------------------------------------
- reg [31 : 0] tmp_read_data;
- reg [31 : 0] tmp_read_data_reg;
reg tmp_error;
reg cipher_init;
@@ -185,7 +186,7 @@ module trng_csprng(
//----------------------------------------------------------------
// Concurrent connectivity for ports etc.
//----------------------------------------------------------------
- assign read_data = tmp_read_data_reg;
+ assign read_data = read_data_reg;
assign error = tmp_error;
assign seed_ack = seed_ack_reg;
assign more_seed = more_seed_reg;
@@ -259,6 +260,7 @@ module trng_csprng(
num_rounds_reg <= DEFAULT_NUM_ROUNDS;
num_blocks_low_reg <= DEFAULT_NUM_BLOCKS[31 : 0];
num_blocks_high_reg <= DEFAULT_NUM_BLOCKS[63 : 32];
+ tmp_read_data_reg <= 32'h00000000;
csprng_ctrl_reg <= CTRL_IDLE;
end
else
@@ -267,60 +269,41 @@ module trng_csprng(
seed_ack_reg <= seed_ack_new;
seed_reg <= seed_new;
+ if (cs)
+ read_data_reg <= read_data_new;
+
if (enable_we)
- begin
- enable_reg <= enable_new;
- end
+ enable_reg <= enable_new;
if (cipher_key_we)
- begin
- cipher_key_reg <= cipher_key_new;
- end
+ cipher_key_reg <= cipher_key_new;
if (cipher_iv_we)
- begin
- cipher_iv_reg <= cipher_iv_new;
- end
+ cipher_iv_reg <= cipher_iv_new;
if (cipher_ctr_we)
- begin
- cipher_ctr_reg <= cipher_ctr_new;
- end
+ cipher_ctr_reg <= cipher_ctr_new;
if (cipher_block_we)
- begin
- cipher_block_reg <= cipher_block_new;
- end
+ cipher_block_reg <= cipher_block_new;
if (block_ctr_we)
- begin
- block_ctr_reg <= block_ctr_new;
- end
+ block_ctr_reg <= block_ctr_new;
if (ready_we)
- begin
- ready_reg <= ready_new;
- end
+ ready_reg <= ready_new;
if (csprng_ctrl_we)
- begin
- csprng_ctrl_reg <= csprng_ctrl_new;
- end
+ csprng_ctrl_reg <= csprng_ctrl_new;
if (num_rounds_we)
- begin
- num_rounds_reg <= num_rounds_new;
- end
+ num_rounds_reg <= num_rounds_new;
if (num_blocks_low_we)
- begin
- num_blocks_low_reg <= num_blocks_low_new;
- end
+ num_blocks_low_reg <= num_blocks_low_new;
if (num_blocks_high_we)
- begin
- num_blocks_high_reg <= num_blocks_high_new;
- end
+ num_blocks_high_reg <= num_blocks_high_new;
end
end // reg_update
@@ -344,7 +327,7 @@ module trng_csprng(
rnd_ack = 0;
- tmp_read_data = 32'h00000000;
+ read_data_new = 32'h00000000;
tmp_error = 0;
if (cs)
@@ -393,33 +376,33 @@ module trng_csprng(
// Read operations.
ADDR_CTRL:
begin
- tmp_read_data = {30'h00000000, seed_reg, enable_reg};
+ read_data_new = {30'h00000000, seed_reg, enable_reg};
end
ADDR_STATUS:
begin
- tmp_read_data = {30'h00000000, ready_reg, rnd_syn};
+ read_data_new = {30'h00000000, ready_reg, rnd_syn};
end
ADDR_RND_DATA:
begin
- tmp_read_data = rnd_data;
+ read_data_new = rnd_data;
rnd_ack = 1;
end
ADDR_NUM_ROUNDS:
begin
- tmp_read_data = {27'h0000000, num_rounds_reg};
+ read_data_new = {27'h0000000, num_rounds_reg};
end
ADDR_NUM_BLOCKS_LOW:
begin
- tmp_read_data = num_blocks_low_reg;
+ read_data_new = num_blocks_low_reg;
end
ADDR_NUM_BLOCKS_HIGH:
begin
- tmp_read_data = num_blocks_high_reg;
+ read_data_new = num_blocks_high_reg;
end
default:
@@ -431,12 +414,6 @@ module trng_csprng(
end
end // cspng_api_logic
- // register data for eim output
- always @(posedge clk)
- begin
- tmp_read_data_reg <= tmp_read_data;
- end
-
//----------------------------------------------------------------
// block_ctr
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