[Cryptech-Commits] [test/coretest_test_core] 07/08: Adding a prebuilt FPGA configuration file for the TerasIC C5G board.

[git at cryptech.is]

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paul at psgd.org pushed a commit to branch master
in repository test/coretest_test_core.

commit ffc02463f8113219c4f9c8940cf28508dabc90c3
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Mar 13 16:20:10 2014 +0100

    Adding a prebuilt FPGA configuration file for the TerasIC C5G board.
---
 .../terasic_c5g/coretest_terasic_c5g_pinlist.txt   |  68 +++++++++++++++++++++
 .../coretest_test_core.sof                         | Bin 0 -> 3993908 bytes
 2 files changed, 68 insertions(+)

diff --git a/toolruns/quartus/terasic_c5g/coretest_terasic_c5g_pinlist.txt b/toolruns/quartus/terasic_c5g/coretest_terasic_c5g_pinlist.txt
new file mode 100644
index 0000000..466ff0f
--- /dev/null
+++ b/toolruns/quartus/terasic_c5g/coretest_terasic_c5g_pinlist.txt
@@ -0,0 +1,68 @@
+#=======================================================================
+#
+# coretest_terasic_c5g_pinlist.txt
+# --------------------------------
+# Pin assignment list for implementing the coretest_test_core system
+# on the TerasIC C5G board. Add these to your qsf-file to connect the
+# ports to the board.
+#
+# 
+# Author: Joachim Strömbergson
+# Copyright (c) 2014 SUNET
+# 
+# Redistribution and use in source and binary forms, with or 
+# without modification, are permitted provided that the following 
+# conditions are met: 
+# 
+# 1. Redistributions of source code must retain the above copyright 
+#    notice, this list of conditions and the following disclaimer. 
+# 
+# 2. Redistributions in binary form must reproduce the above copyright 
+#    notice, this list of conditions and the following disclaimer in 
+#    the documentation and/or other materials provided with the 
+#    distribution. 
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#=======================================================================
+
+set_location_assignment PIN_R20 -to clk
+set_location_assignment PIN_P11 -to reset_n
+set_location_assignment PIN_M9 -to rxd
+set_location_assignment PIN_L9 -to txd
+set_location_assignment PIN_L7 -to debug[0]
+set_location_assignment PIN_K6 -to debug[1]
+set_location_assignment PIN_D8 -to debug[2]
+set_location_assignment PIN_E9 -to debug[3]
+set_location_assignment PIN_A5 -to debug[4]
+set_location_assignment PIN_B6 -to debug[5]
+set_location_assignment PIN_H8 -to debug[6]
+set_location_assignment PIN_H9 -to debug[7]
+set_instance_assignment -name IO_STANDARD "3.3-V LVTTL" -to clk
+set_instance_assignment -name IO_STANDARD "1.2 V" -to reset_n
+set_instance_assignment -name IO_STANDARD "2.5 V" -to rxd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to txd
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[0]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[1]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[2]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[3]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[4]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[5]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[6]
+set_instance_assignment -name IO_STANDARD "2.5 V" -to debug[7]
+
+#=======================================================================
+# EOF coretest_terasic_c5g_pinlist.txt
+#=======================================================================
+
diff --git a/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_test_core.sof b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_test_core.sof
new file mode 100644
index 0000000..90419b0
Binary files /dev/null and b/toolruns/quartus/terasic_c5g/cryptech_pre_build_image/coretest_test_core.sof differ