[Cryptech-Commits] [staging/core/hash/sha256] 16/32: Updated status with info on the sliding window W-mem and the new implementation results.

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paul at psgd.org pushed a commit to branch master
in repository staging/core/hash/sha256.

commit 9f03046a6640212a45e8f5deac6a640a18d9f6b4
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sat Feb 22 08:08:47 2014 +0100

    Updated status with info on the sliding window W-mem and the new implementation results.
---
 README.md | 55 ++++++++++++++++++++++++++++++++++++++++++++++++++++---
 1 file changed, 52 insertions(+), 3 deletions(-)

diff --git a/README.md b/README.md
index c17722f..1171832 100644
--- a/README.md
+++ b/README.md
@@ -13,21 +13,70 @@ written in Python.
 
 
 ## Implementation ##
+
+The W-memory scheduler is based on 16 32-bit registers. Thee registers
+are loaded with the current block. After 16 rounds the contents of the
+registers slide through the registers r5..r0 while the new W word is
+inserted at r15 as well as being returned to the core.
+
+
+### Cyclone IV E ###
 Implementation results using the Altera Quartus-II v13.1 design tool.
 
+Device: Cyclone IV E - EP4CE6F17C6
+- 3765 LEs
+- 1813 registers
+- 76 MHz
+- 66 cycles latency
+
+
 ### Cyclone IV GX ###
-- 9587 LEs
-- 3349 registers
-- 73 MHz
+Implementation results using the Altera Quartus-II v13.1 design tool.
+
+Device: Cyclone IV GX - EP4CGX22CF19C6
+- 3765 LEs
+- 1813 registers
+- 76 MHz
 - 66 cycles latency
 
 
+### Cyclone V GX ###
+Implementation results using the Altera Quartus-II v13.1 design tool.
+
+Device: Cyclone V GX - 5CGXFC7C7F23C8
+- 1456 ALMs
+- 1813 registers
+- 78 MHz
+- 66 cycles latency
+
+
+
+
 ## Todo ##
 - Extensive verification in physical device.
 - Complete documentation.
 
 
 ## Status ##
+**(2014-02-22)**
+
+Redesigned the W-memory into a sliding window solution. This not only
+removed 48 32-registers but also several muxes and address decoders.
+
+The old implementation resources and performance:
+- 9587 LEs
+- 3349 registers
+- 73 MHz
+- 66 cycles latency
+
+The new implementation resources and performance:
+- 3765 LEs
+- 1813 registers
+- 76 MHz
+- 66 cycles latency
+
+
+
 **(2014-02-19)**
 - The core has been added to the Cryptech repo. The core comes from
   https://github.com/secworks/sha256