[Cryptech-Commits] [staging/core/platform/terasic_c5g] branch master created (now 3c36fb8)

[git at cryptech.is]

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paul at psgd.org pushed a change to branch master
in repository staging/core/platform/terasic_c5g.

        at  3c36fb8   Rearrange cores.

This branch includes the following new commits:

       new  e19e830   Adding readme and license for the coretest_hashes subsystem.
       new  6f6ab17   Adding RTL to build the coretest_hashes subsystem with SHA-1 and SHA-256 cores.
       new  d9fb29d   Adding Makefile to build the coretest_hashes subsystem.
       new  9a275f8   Updating address for uart to 8 bits which should be the default.
       new  6ff77cf   Adding test program that checks the SHA-1 and SHA-256 cores and do single block hashing.
       new  2608109   Adding bitstream file for coretest_hashes on the TerasIC C5G board.
       new  fca501d   Adding project, assignment and clock setup files for Quartus and the TerasIC C5G board.
       new  5705e46   Refactored code to allow additions of test cases. Adding dual block message test cases as specified by NIST. Adding code for running huge message test. This test case si disabled due to bugs in coretest.
       new  a32a3fe   Update of prebuilt FPGA configuration with new coretest.
       new  9dd5384   Update of coretest_hashes to also include the sha512 core.
       new  1b09794   Adding prebuilt coretest_hashes that includes SHA-512.
       new  a8d3dcb   (1) Added functionality to do single block tests of all SHA-512/x modes. (2) Major cleanup of nits and magic constants. Moved all test cases to separate functions. Added support to enable/disable tests.
       new  4d75110   Adding test case for dual block tests of SHA-512/x. All tests passed. Separated delays into comm vs processing. Updated comment in header to reflect SHA-512/x.
       new  754458f   Fixed error in (c). Drastically reduced processing delay. Adding missing expected digest for SHA-384.
       new  f4ac04e   Added functionality to change baud rate. Decreased comm delay. Now test cases goes much faster.
       new  3215511   Adding new prebuilt FPGA with uart that supports change of bitrate.
       new  7c3d902   Enabling all test cases again.
       new  ab81987   Fixed huge message test. We now run test of message with 100 blocks in SHA-256.
       new  e61ac3e   Increased communication speed. Increased number of blocks in huge mesage test to 1000 blocks.
       new  3c36fb8   Rearrange cores.

The 20 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "adds" were already present in the repository and have only
been added to this reference.