August 2017 Archives by subject

• Messages sorted by: [ thread ] [ author ] [ date ]
• More info on this list...

Starting: Sun Aug 6 18:41:49 UTC 2017
Ending: Tue Aug 22 18:59:18 UTC 2017
Messages: 42

• [Cryptech-Commits] [core/math/modexpa7] 01/01: Adding CRT support...   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/01: Work in progress.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/03: CRT mode seems to work. Finally.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/03: Minor cleanup, removed unused flag register 'shreg_now_latency'.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 03/03: Minor cleanup.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt created (now c61d70d)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt created (now e480401)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt deleted (was c61d70d)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt updated (e480401 -> 1cb1e70)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt updated: Added some info to the README file.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic_crt updated: Added STM32 code to test CRT mode in hardware.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: * Added readme file * Enabled vendor-specific primitive usage for compilation   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: * Moved systolic processing element array into a separate module. * Finished top-level wrapper module.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prevent clashes with low-level modules in ECDSA multipliers.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Added demo program that shows how to talk to the core and sign something.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] tag v0.20 created (now 06dadb7)   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] 01/01: Update modexpa7 path names for systolic branch.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic created (now c67c61b)   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic updated: Allow core instantation parameters.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic updated: Don't try to synthesize include files.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic updated: Drop duplicate bram_1rw_1ro_readfirst module.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic updated: reset_n vs rst_n, pax guys.   git at cryptech.is
• [Cryptech-Commits] [core/platform/common] branch systolic updated: Update modexpa7 filenames.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] 01/01: Preliminary build with Pavel's new "systolic" ModExp core.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch master updated: Drag in Paul's UART reliability fixes.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic created (now 2a07970)   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: Don't try to synthesize include files.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: Drop duplicate bram_1rw_1ro_readfirst module.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: reset_n vs rst_n, pax guys.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: Systolic ModExpA7 core instantiation parameters.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: Update modexpa7 filenames.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch systolic updated: Update Verilog source file list to match systolic modexp core.   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] branch master updated: Unconditionally set the allocated flag when initializing a hash state structure.   git at cryptech.is
• [Cryptech-Commits] [sw/stm32] 01/03: Add a generic SysTick hook, to call a function on every 1ms tick, because it's easier than setting up a dedicated timer.   git at cryptech.is
• [Cryptech-Commits] [sw/stm32] 02/03: Adapt uart_rx_thread to the post-thread tasking model, because we're still subject to the same forces that made it a good idea in the first place.   git at cryptech.is
• [Cryptech-Commits] [sw/stm32] 03/03: Report UART receive queue length, so we can tune it.   git at cryptech.is
• [Cryptech-Commits] [sw/stm32] branch master updated (0d33ff8 -> 8b4fd99)   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Cosmetic changes.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Follow what Verilog does more closely.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Generate additional quantities required for testing of CRT in hardware.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Renamed some of the test vector components for improved consistency.   git at cryptech.is
• [Cryptech-Commits] [user/sra/aes-keywrap] branch master updated: Old simplification, never committed.   git at cryptech.is

Last message date: Tue Aug 22 18:59:18 UTC 2017
Archived on: Tue Aug 22 18:59:22 UTC 2017

• Messages sorted by: [ thread ] [ author ] [ date ]
• More info on this list...