[Cryptech-Commits] [core/platform/common] branch systolic updated: Allow core instantation parameters.

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sra at hactrn.net pushed a commit to branch systolic
in repository core/platform/common.

The following commit(s) were added to refs/heads/systolic by this push:
     new a33644a  Allow core instantation parameters.
a33644a is described below

commit a33644a8ad3ba8c4baed3ecf60999fb5ab966be9
Author: Rob Austein <sra at hactrn.net>
AuthorDate: Tue Aug 8 16:09:44 2017 -0400

    Allow core instantation parameters.
---
 config/core.cfg       |  4 ++++
 config/core_config.py | 16 ++++++++++++++--
 2 files changed, 18 insertions(+), 2 deletions(-)

diff --git a/config/core.cfg b/config/core.cfg
index 58ce075..6b71fac 100644
--- a/config/core.cfg
+++ b/config/core.cfg
@@ -121,6 +121,8 @@ cores = mkmif trng sha1 sha1 sha1 sha256 sha256 sha256 sha512 sha512 sha512 aes
 # extra ports: Extra port definitions in the core instance.
 #   Note this is a blob of text, not interpreted, so formatting and commas
 #   will be copied out verbatim.
+#
+# parameter XXXX: parameter to be passed when instantiating core.
 
 [core sha1]
 vfiles =
@@ -187,6 +189,8 @@ core blocks = 4
 block memory = yes
 error wire = no
 module name = modexpa7_wrapper
+parameter OPERAND_ADDR_WIDTH = 7
+parameter SYSTOLIC_ARRAY_POWER = 1
 vfiles =
 	math/modexpa7/src/rtl/modexpa7_exponentiator.v
 	math/modexpa7/src/rtl/modexpa7_factor.v
diff --git a/config/core_config.py b/config/core_config.py
index 3f75243..4de8f16 100755
--- a/config/core_config.py
+++ b/config/core_config.py
@@ -235,6 +235,11 @@ class Core(object):
         self.dummy = cfg.get(self.cfg_section, "dummy")
         if self.dummy:
             self.dummy = self.dummy.replace("\n", "\n   ") + "\n"
+        self._parameters = dict()
+        if cfg.has_section(self.cfg_section):
+            for option in cfg.options(self.cfg_section):
+                if option.startswith("parameter "):
+                    self._parameters[option[len("parameter"):].upper().strip()] = cfg.get(self.cfg_section, option)
 
     @property
     def instance_name(self):
@@ -274,6 +279,13 @@ class Core(object):
     def mux_error_reg(self):
         return "error_" + self.instance_name if self.error_wire else "0"
 
+    @property
+    def parameters(self):
+        if self._parameters:
+            return "#( {} ) ".format(", ".join(".{} ({})".format(k, v) for k, v in self._parameters.iteritems()))
+        else:
+            return ""
+
     def createInstance(self):
         template = createInstance_template_dummy if self.dummy else createInstance_template_generic if self.blocks == 1 else createInstance_template_multi_block
         return template.format(core = self)
@@ -325,7 +337,7 @@ createInstance_template_generic = """\
    wire                 enable_{core.instance_name} = (addr_core_num == CORE_ADDR_{core.upper_instance_name});
    wire [31: 0]         read_data_{core.instance_name};{core.error_wire_decl}
 
-   {core.module_name} {core.instance_name}_inst
+   {core.module_name} {core.parameters}{core.instance_name}_inst
      (
       .clk(sys_clk),
       .reset_n(sys_rst_n),
@@ -353,7 +365,7 @@ createInstance_template_multi_block = """\
    wire [31: 0]         read_data_{core.instance_name};{core.error_wire_decl}
    wire [{core.block_bit_max}:0]           {core.instance_name}_prefix = addr_core_num[{core.block_bit_max}:0] - CORE_ADDR_{core.upper_instance_name};
 
-   {core.module_name} {core.instance_name}_inst
+   {core.module_name} {core.parameters}{core.instance_name}_inst
      (
       .clk(sys_clk),
       .reset_n(sys_rst_n),

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