[Cryptech-Commits] [releng/alpha] branch systolic updated: Update Verilog source file list to match systolic modexp core.

[git at cryptech.is]

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sra at hactrn.net pushed a commit to branch systolic
in repository releng/alpha.

The following commit(s) were added to refs/heads/systolic by this push:
     new 7d1c7fb  Update Verilog source file list to match systolic modexp core.
7d1c7fb is described below

commit 7d1c7fb925ea5036520b106e54aaece4fc50a41a
Author: Rob Austein <sra at hactrn.net>
AuthorDate: Tue Aug 8 11:03:13 2017 -0400

    Update Verilog source file list to match systolic modexp core.
---
 .gitmodules                 | 1 +
 source/core/platform/common | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/.gitmodules b/.gitmodules
index 790b2ac..3a6f269 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -71,3 +71,4 @@
 [submodule "source/core/platform/common"]
 	path = source/core/platform/common
 	url = https://git.cryptech.is/core/platform/common.git
+	branch = systolic
diff --git a/source/core/platform/common b/source/core/platform/common
index 4cf0453..c67c61b 160000
--- a/source/core/platform/common
+++ b/source/core/platform/common
@@ -1 +1 @@
-Subproject commit 4cf0453270038d4fc50dcad293caef34f474d7e3
+Subproject commit c67c61b12454d6cd484a67db01814f5707724cf4

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