[Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Follow what Verilog does more closely.

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meisterpaul1 at yandex.ru pushed a commit to branch master
in repository user/shatov/modexp_fpga_model.

The following commit(s) were added to refs/heads/master by this push:
     new 91cdd1b  Follow what Verilog does more closely.
91cdd1b is described below

commit 91cdd1b39e10a604719a030c98a2339ab3164941
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Sun Aug 6 21:41:03 2017 +0300

    Follow what Verilog does more closely.
---
 modexp_fpga_model_montgomery.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/modexp_fpga_model_montgomery.cpp b/modexp_fpga_model_montgomery.cpp
index 92a5e47..7455b23 100644
--- a/modexp_fpga_model_montgomery.cpp
+++ b/modexp_fpga_model_montgomery.cpp
@@ -85,9 +85,9 @@ void montgomery_multiply(const FPGA_WORD *A, const FPGA_WORD *B, const FPGA_WORD
 		for (i=0; i<(2*len); i++)
 			AB[i] = A[i];
 
-	if (!reduce_only)	multiply_systolic(A,  B,       AB, len, 2 * len);		// AB = A  * B
-						multiply_systolic(AB, N_COEFF, Q,  len,     len);		// Q  = AB * N_COEFF
-						multiply_systolic(Q,  N,       QN, len, 2 * len);		// QN = Q * N
+	if (!reduce_only)	multiply_systolic(A,       B,  AB, len, 2 * len);		// AB = A  * B
+						multiply_systolic(N_COEFF, AB, Q,  len,     len);		// Q  = AB * N_COEFF
+						multiply_systolic(Q,       N,  QN, len, 2 * len);		// QN = Q * N
 
 		// initialize 1-bit carry and borrow
 	c_in_s = 0, b_in_sn = 0;

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