[Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prevent clashes with low-level modules in ECDSA multipliers.
git at cryptech.is
git at cryptech.is
Wed Aug 9 13:18:22 UTC 2017
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meisterpaul1 at yandex.ru pushed a commit to branch systolic
in repository core/math/modexpa7.
The following commit(s) were added to refs/heads/systolic by this push:
new a44bbd3 Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prevent clashes with low-level modules in ECDSA multipliers.
a44bbd3 is described below
commit a44bbd3fe1088201401430079f8af52b207eece6
Author: Pavel V. Shatov (Meister) <meisterpaul1 at yandex.ru>
AuthorDate: Wed Aug 9 16:13:45 2017 +0300
Added 'modexpa7_' prefix to all the low-level modules in /src/rtl/pe/ to prevent clashes
with low-level modules in ECDSA multipliers.
We should consolidate all the lowel-level stuff across all the math cores in the future.
---
...{adder32_artix7.v => modexpa7_adder32_artix7.v} | 122 ++++----
...sp48e1_wrapper.v => modexpa7_dsp48e1_wrapper.v} | 60 ++--
...rapper_ext.v => modexpa7_dsp48e1_wrapper_ext.v} | 60 ++--
...r32_artix7.v => modexpa7_multiplier32_artix7.v} | 338 ++++++++++-----------
...r32_artix7.v => modexpa7_subtractor32_artix7.v} | 190 ++++++------
...c_pe_artix7.v => modexpa7_systolic_pe_artix7.v} | 180 +++++------
...dder32_generic.v => modexpa7_adder32_generic.v} | 58 ++--
...2_generic.v => modexpa7_subtractor32_generic.v} | 136 ++++-----
...pe_generic.v => modexpa7_systolic_pe_generic.v} | 170 +++++------
src/rtl/pe/modexpa7_primitive_switch.v | 12 +-
10 files changed, 663 insertions(+), 663 deletions(-)
diff --git a/src/rtl/pe/artix7/adder32_artix7.v b/src/rtl/pe/artix7/modexpa7_adder32_artix7.v
similarity index 95%
rename from src/rtl/pe/artix7/adder32_artix7.v
rename to src/rtl/pe/artix7/modexpa7_adder32_artix7.v
index 6da5bd9..e0ff080 100644
--- a/src/rtl/pe/artix7/adder32_artix7.v
+++ b/src/rtl/pe/artix7/modexpa7_adder32_artix7.v
@@ -1,8 +1,8 @@
//------------------------------------------------------------------------------
//
-// adder32_artix7.v
+// modexpa7_adder32_artix7.v
// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit adder.
+// Hardware (Artix-7 DSP48E1) 32-bit adder.
//
// Authors: Pavel Shatov
//
@@ -34,64 +34,64 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
-//------------------------------------------------------------------------------
-
-module adder32_artix7
- (
- input clk, // clock
- input ce, // clock enable
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
-
- //
- // Lower and higher parts of operand
- //
- wire [17: 0] bl = b[17: 0];
- wire [13: 0] bh = b[31:18];
-
-
- //
- // DSP48E1 Slice
- //
-
- /* Operation Mode */
- wire [ 3: 0] dsp48e1_alumode = 4'b0000;
- wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
-
- /* Internal Product */
- wire [47: 0] p_int;
-
- dsp48e1_wrapper dsp_adder
- (
- .clk (clk),
-
- .ce (ce),
-
- .carry (c_in),
-
- .alumode (dsp48e1_alumode),
- .opmode (dsp48e1_opmode),
-
- .a ({{16{1'b0}}, bh}),
- .b (bl),
- .c ({{16{1'b0}}, a}),
-
- .p (p_int)
- );
-
- //
- // Output Mapping
- //
- assign s = p_int[31: 0];
- assign c_out = p_int[32];
-
-
-endmodule
-
+//------------------------------------------------------------------------------
+
+module modexpa7_adder32_artix7
+ (
+ input clk, // clock
+ input ce, // clock enable
+ input [31: 0] a, // operand input
+ input [31: 0] b, // operand input
+ output [31: 0] s, // sum output
+ input c_in, // carry input
+ output c_out // carry output
+ );
+
+ //
+ // Lower and higher parts of operand
+ //
+ wire [17: 0] bl = b[17: 0];
+ wire [13: 0] bh = b[31:18];
+
+
+ //
+ // DSP48E1 Slice
+ //
+
+ /* Operation Mode */
+ wire [ 3: 0] dsp48e1_alumode = 4'b0000;
+ wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
+
+ /* Internal Product */
+ wire [47: 0] p_int;
+
+ modexpa7_dsp48e1_wrapper dsp_adder
+ (
+ .clk (clk),
+
+ .ce (ce),
+
+ .carry (c_in),
+
+ .alumode (dsp48e1_alumode),
+ .opmode (dsp48e1_opmode),
+
+ .a ({{16{1'b0}}, bh}),
+ .b (bl),
+ .c ({{16{1'b0}}, a}),
+
+ .p (p_int)
+ );
+
+ //
+ // Output Mapping
+ //
+ assign s = p_int[31: 0];
+ assign c_out = p_int[32];
+
+
+endmodule
+
//------------------------------------------------------------------------------
// End-of-File
-//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/dsp48e1_wrapper.v b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v
similarity index 98%
rename from src/rtl/pe/artix7/dsp48e1_wrapper.v
rename to src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v
index 11a21bc..1d6b721 100644
--- a/src/rtl/pe/artix7/dsp48e1_wrapper.v
+++ b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper.v
@@ -1,8 +1,8 @@
//------------------------------------------------------------------------------
//
-// dsp48e1_wrapper.v
+// modexpa7_dsp48e1_wrapper.v
// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) tile wrapper.
+// Hardware (Artix-7 DSP48E1) tile wrapper.
//
// Authors: Pavel Shatov
//
@@ -34,30 +34,30 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
-//------------------------------------------------------------------------------
-
-module dsp48e1_wrapper
- (
- input clk,
-
- input ce,
-
- input [ 6: 0] opmode,
- input [ 3: 0] alumode,
-
- input carry,
-
- input [29: 0] a,
- input [17: 0] b,
- input [47: 0] c,
-
- output [47: 0] p
- );
-
-
- //
- // Tile instantiation
- //
+//------------------------------------------------------------------------------
+
+module modexpa7_dsp48e1_wrapper
+ (
+ input clk,
+
+ input ce,
+
+ input [ 6: 0] opmode,
+ input [ 3: 0] alumode,
+
+ input carry,
+
+ input [29: 0] a,
+ input [17: 0] b,
+ input [47: 0] c,
+
+ output [47: 0] p
+ );
+
+
+ //
+ // Tile instantiation
+ //
DSP48E1 #
(
.AREG (0),
@@ -66,7 +66,7 @@ module dsp48e1_wrapper
.DREG (0),
.MREG (0),
.PREG (1),
- .ADREG (0),
+ .ADREG (0),
.ACASCREG (0),
.BCASCREG (0),
@@ -77,7 +77,7 @@ module dsp48e1_wrapper
.CARRYINSELREG (0),
.A_INPUT ("DIRECT"),
- .B_INPUT ("DIRECT"),
+ .B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("DYNAMIC"),
@@ -155,5 +155,5 @@ module dsp48e1_wrapper
.BCOUT (),
.PCOUT ()
);
-
-endmodule
+
+endmodule
diff --git a/src/rtl/pe/artix7/dsp48e1_wrapper_ext.v b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v
similarity index 97%
rename from src/rtl/pe/artix7/dsp48e1_wrapper_ext.v
rename to src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v
index 83fb78c..bf0758c 100644
--- a/src/rtl/pe/artix7/dsp48e1_wrapper_ext.v
+++ b/src/rtl/pe/artix7/modexpa7_dsp48e1_wrapper_ext.v
@@ -1,8 +1,8 @@
//------------------------------------------------------------------------------
//
-// dsp48e1_wrapper_ext.v
+// modexpa7_dsp48e1_wrapper_ext.v
// -----------------------------------------------------------------------------
-// Extended hardware (Artix-7 DSP48E1) tile wrapper.
+// Extended hardware (Artix-7 DSP48E1) tile wrapper.
//
// Authors: Pavel Shatov
//
@@ -34,30 +34,30 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
-//------------------------------------------------------------------------------
-
-module dsp48e1_wrapper_ext #
- (
- parameter AREG = 1'b0,
- parameter PREG = 1'b0,
-
- parameter A_INPUT = "DIRECT"
- )
- (
- input clk,
- input [ 6: 0] opmode,
- input [29: 0] a,
- input [17: 0] b,
- output [47: 0] p,
- input [29: 0] acin,
- input [47: 0] pcin,
- output [29: 0] acout,
- output [47: 0] pcout
- );
-
- //
- // Tile instantiation
- //
+//------------------------------------------------------------------------------
+
+module modexpa7_dsp48e1_wrapper_ext #
+ (
+ parameter AREG = 1'b0,
+ parameter PREG = 1'b0,
+
+ parameter A_INPUT = "DIRECT"
+ )
+ (
+ input clk,
+ input [ 6: 0] opmode,
+ input [29: 0] a,
+ input [17: 0] b,
+ output [47: 0] p,
+ input [29: 0] acin,
+ input [47: 0] pcin,
+ output [29: 0] acout,
+ output [47: 0] pcout
+ );
+
+ //
+ // Tile instantiation
+ //
DSP48E1 #
(
.AREG (AREG),
@@ -66,7 +66,7 @@ module dsp48e1_wrapper_ext #
.DREG (0),
.MREG (0),
.PREG (PREG),
- .ADREG (0),
+ .ADREG (0),
.ACASCREG (AREG),
.BCASCREG (1'b1),
@@ -77,7 +77,7 @@ module dsp48e1_wrapper_ext #
.CARRYINSELREG (0),
.A_INPUT (A_INPUT),
- .B_INPUT ("DIRECT"),
+ .B_INPUT ("DIRECT"),
.USE_DPORT ("FALSE"),
.USE_MULT ("MULTIPLY"),
@@ -155,5 +155,5 @@ module dsp48e1_wrapper_ext #
.BCOUT (),
.PCOUT (pcout)
);
-
-endmodule
+
+endmodule
diff --git a/src/rtl/pe/artix7/multiplier32_artix7.v b/src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v
similarity index 92%
rename from src/rtl/pe/artix7/multiplier32_artix7.v
rename to src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v
index 1fc6d30..40cdece 100644
--- a/src/rtl/pe/artix7/multiplier32_artix7.v
+++ b/src/rtl/pe/artix7/modexpa7_multiplier32_artix7.v
@@ -1,171 +1,171 @@
-//------------------------------------------------------------------------------
-//
-// multiplier32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit multiplier.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module multiplier32_artix7
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- output [63: 0] p
- );
-
- /* split a, b into smaller words */
- wire [16: 0] a_lo = a[16: 0];
- wire [16: 0] b_lo = b[16: 0];
- wire [14: 0] a_hi = a[31:17];
- wire [14: 0] b_hi = b[31:17];
-
- /* smaller sub-products */
- wire [47: 0] dsp1_p;
- wire [47: 0] dsp2_p;
- wire [47: 0] dsp4_p;
-
- /* direct output mapping */
- assign p[63:34] = dsp4_p[29: 0];
-
- /* delayed output mapping */
- genvar fd;
- generate for (fd=0; fd<17; fd=fd+1)
- begin : gen_FD
+//------------------------------------------------------------------------------
+//
+// modexpa7_multiplier32_artix7.v
+// -----------------------------------------------------------------------------
+// Hardware (Artix-7 DSP48E1) 32-bit multiplier.
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2016-2017, NORDUnet A/S
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may be
+// used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//------------------------------------------------------------------------------
+
+module modexpa7_multiplier32_artix7
+ (
+ input clk,
+ input [31: 0] a,
+ input [31: 0] b,
+ output [63: 0] p
+ );
+
+ /* split a, b into smaller words */
+ wire [16: 0] a_lo = a[16: 0];
+ wire [16: 0] b_lo = b[16: 0];
+ wire [14: 0] a_hi = a[31:17];
+ wire [14: 0] b_hi = b[31:17];
+
+ /* smaller sub-products */
+ wire [47: 0] dsp1_p;
+ wire [47: 0] dsp2_p;
+ wire [47: 0] dsp4_p;
+
+ /* direct output mapping */
+ assign p[63:34] = dsp4_p[29: 0];
+
+ /* delayed output mapping */
+ genvar fd;
+ generate for (fd=0; fd<17; fd=fd+1)
+ begin : gen_FD
FD # (.INIT( 1'b0)) FD_inst1 (.C(clk), .D(dsp1_p[fd]), .Q(p[fd + 0]));
- FD # (.INIT( 1'b0)) FD_inst3 (.C(clk), .D(dsp2_p[fd]), .Q(p[fd + 17]));
- end
- endgenerate
-
- /* product chains */
- wire [47: 0] dsp1_p_chain;
- wire [47: 0] dsp3_p_chain;
- wire [47: 0] dsp2_p_chain;
-
- /* operand chains */
- wire [29: 0] a_lo_chain;
+ FD # (.INIT( 1'b0)) FD_inst3 (.C(clk), .D(dsp2_p[fd]), .Q(p[fd + 17]));
+ end
+ endgenerate
+
+ /* product chains */
+ wire [47: 0] dsp1_p_chain;
+ wire [47: 0] dsp3_p_chain;
+ wire [47: 0] dsp2_p_chain;
+
+ /* operand chains */
+ wire [29: 0] a_lo_chain;
wire [29: 0] a_hi_chain;
-
- //
- // a_lo * b_lo
- //
- dsp48e1_wrapper_ext #
- (
- .AREG (1'b1),
- .PREG (1'b0),
- .A_INPUT ("DIRECT")
- )
- dsp1
- (
- .clk (clk),
- .opmode (7'b0110101),
- .a ({13'd0, a_lo}),
- .b ({1'b0, b_lo}),
- .p (dsp1_p),
- .acin (30'd0),
- .pcin (48'd0),
- .acout (a_lo_chain),
- .pcout (dsp1_p_chain)
- );
-
- //
- // a_hi * b_lo
- //
- dsp48e1_wrapper_ext #
- (
- .AREG (1'b1),
- .PREG (1'b0),
- .A_INPUT ("DIRECT")
- )
- dsp2
- (
- .clk (clk),
- .opmode (7'b0010101),
- .a ({15'd0, a_hi}),
- .b ({1'd0, b_lo}),
- .p (dsp2_p),
- .acin (30'd0),
- .pcin (dsp3_p_chain),
- .acout (a_hi_chain),
- .pcout (dsp2_p_chain)
- );
-
- //
- // a_lo * b_hi
- //
- dsp48e1_wrapper_ext #
- (
- .AREG (1'b0),
- .PREG (1'b0),
- .A_INPUT ("CASCADE")
- )
- dsp3
- (
- .clk (clk),
- .opmode (7'b1010101),
- .a (30'd0),
- .b ({3'd0, b_hi}),
- .p (),
- .acin (a_lo_chain),
- .pcin (dsp1_p_chain),
- .acout (),
- .pcout (dsp3_p_chain)
- );
-
- //
- // a_hi * b_hi
- //
- dsp48e1_wrapper_ext #
- (
- .AREG (1'b0),
- .PREG (1'b1),
- .A_INPUT ("CASCADE")
- )
- dsp4
- (
- .clk (clk),
- .opmode (7'b1010101),
- .a (30'd0),
- .b ({3'd0, b_hi}),
- .p (dsp4_p),
- .acin (a_hi_chain),
- .pcin (dsp2_p_chain),
- .acout (),
- .pcout ()
- );
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
+
+ //
+ // a_lo * b_lo
+ //
+ modexpa7_dsp48e1_wrapper_ext #
+ (
+ .AREG (1'b1),
+ .PREG (1'b0),
+ .A_INPUT ("DIRECT")
+ )
+ dsp1
+ (
+ .clk (clk),
+ .opmode (7'b0110101),
+ .a ({13'd0, a_lo}),
+ .b ({1'b0, b_lo}),
+ .p (dsp1_p),
+ .acin (30'd0),
+ .pcin (48'd0),
+ .acout (a_lo_chain),
+ .pcout (dsp1_p_chain)
+ );
+
+ //
+ // a_hi * b_lo
+ //
+ modexpa7_dsp48e1_wrapper_ext #
+ (
+ .AREG (1'b1),
+ .PREG (1'b0),
+ .A_INPUT ("DIRECT")
+ )
+ dsp2
+ (
+ .clk (clk),
+ .opmode (7'b0010101),
+ .a ({15'd0, a_hi}),
+ .b ({1'd0, b_lo}),
+ .p (dsp2_p),
+ .acin (30'd0),
+ .pcin (dsp3_p_chain),
+ .acout (a_hi_chain),
+ .pcout (dsp2_p_chain)
+ );
+
+ //
+ // a_lo * b_hi
+ //
+ modexpa7_dsp48e1_wrapper_ext #
+ (
+ .AREG (1'b0),
+ .PREG (1'b0),
+ .A_INPUT ("CASCADE")
+ )
+ dsp3
+ (
+ .clk (clk),
+ .opmode (7'b1010101),
+ .a (30'd0),
+ .b ({3'd0, b_hi}),
+ .p (),
+ .acin (a_lo_chain),
+ .pcin (dsp1_p_chain),
+ .acout (),
+ .pcout (dsp3_p_chain)
+ );
+
+ //
+ // a_hi * b_hi
+ //
+ modexpa7_dsp48e1_wrapper_ext #
+ (
+ .AREG (1'b0),
+ .PREG (1'b1),
+ .A_INPUT ("CASCADE")
+ )
+ dsp4
+ (
+ .clk (clk),
+ .opmode (7'b1010101),
+ .a (30'd0),
+ .b ({3'd0, b_hi}),
+ .p (dsp4_p),
+ .acin (a_hi_chain),
+ .pcin (dsp2_p_chain),
+ .acout (),
+ .pcout ()
+ );
+
+endmodule
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/subtractor32_artix7.v b/src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v
similarity index 93%
rename from src/rtl/pe/artix7/subtractor32_artix7.v
rename to src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v
index 76e10c0..2241f24 100644
--- a/src/rtl/pe/artix7/subtractor32_artix7.v
+++ b/src/rtl/pe/artix7/modexpa7_subtractor32_artix7.v
@@ -1,95 +1,95 @@
-//------------------------------------------------------------------------------
-//
-// subtractor32_artix7.v
-// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) 32-bit subtractor.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module subtractor32_artix7
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- output [31: 0] d,
- input b_in,
- output b_out
- );
-
- //
- // Lower and higher parts of operand
- //
- wire [17: 0] bl = b[17: 0];
- wire [13: 0] bh = b[31:18];
-
- //
- // DSP48E1 Slice
- //
-
- /* Operation Mode */
- wire [ 3: 0] dsp48e1_alumode = 4'b0011;
- wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
-
- /* Internal Product */
- wire [47: 0] p_int;
-
- dsp48e1_wrapper dsp_subtractor
- (
- .clk (clk),
-
- .ce (ce),
-
- .carry (b_in),
-
- .alumode (dsp48e1_alumode),
- .opmode (dsp48e1_opmode),
-
- .a ({{16{1'b0}}, bh}),
- .b (bl),
- .c ({{16{1'b0}}, a}),
-
- .p (p_int)
- );
-
- //
- // Output Mapping
- //
- assign d = p_int[31: 0];
- assign b_out = p_int[32];
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+//
+// modexpa7_subtractor32_artix7.v
+// -----------------------------------------------------------------------------
+// Hardware (Artix-7 DSP48E1) 32-bit subtractor.
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2016-2017, NORDUnet A/S
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may be
+// used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//------------------------------------------------------------------------------
+
+module modexpa7_subtractor32_artix7
+ (
+ input clk,
+ input ce,
+ input [31: 0] a,
+ input [31: 0] b,
+ output [31: 0] d,
+ input b_in,
+ output b_out
+ );
+
+ //
+ // Lower and higher parts of operand
+ //
+ wire [17: 0] bl = b[17: 0];
+ wire [13: 0] bh = b[31:18];
+
+ //
+ // DSP48E1 Slice
+ //
+
+ /* Operation Mode */
+ wire [ 3: 0] dsp48e1_alumode = 4'b0011;
+ wire [ 6: 0] dsp48e1_opmode = 7'b0110011;
+
+ /* Internal Product */
+ wire [47: 0] p_int;
+
+ modexpa7_dsp48e1_wrapper dsp_subtractor
+ (
+ .clk (clk),
+
+ .ce (ce),
+
+ .carry (b_in),
+
+ .alumode (dsp48e1_alumode),
+ .opmode (dsp48e1_opmode),
+
+ .a ({{16{1'b0}}, bh}),
+ .b (bl),
+ .c ({{16{1'b0}}, a}),
+
+ .p (p_int)
+ );
+
+ //
+ // Output Mapping
+ //
+ assign d = p_int[31: 0];
+ assign b_out = p_int[32];
+
+endmodule
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/artix7/systolic_pe_artix7.v b/src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v
similarity index 93%
rename from src/rtl/pe/artix7/systolic_pe_artix7.v
rename to src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v
index b29f2c0..881e583 100644
--- a/src/rtl/pe/artix7/systolic_pe_artix7.v
+++ b/src/rtl/pe/artix7/modexpa7_systolic_pe_artix7.v
@@ -1,8 +1,8 @@
//------------------------------------------------------------------------------
//
-// systolic_pe_artix7.v
+// modexpa7_systolic_pe_artix7.v
// -----------------------------------------------------------------------------
-// Hardware (Artix-7 DSP48E1) low-level systolic array processing element.
+// Hardware (Artix-7 DSP48E1) low-level systolic array processing element.
//
// Authors: Pavel Shatov
//
@@ -34,93 +34,93 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
-//------------------------------------------------------------------------------
-
-module systolic_pe_artix7
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- input [31: 0] t,
- input [31: 0] c_in,
- output [31: 0] p,
- output [31: 0] c_out
- );
-
- reg [31: 0] t_dly;
- reg [31: 0] c_in_dly;
-
- always @(posedge clk) t_dly <= t;
- always @(posedge clk) c_in_dly <= c_in;
-
- wire [31: 0] t_c_in_s;
- wire t_c_in_c_out;
-
- reg t_c_in_c_out_dly;
-
- always @(posedge clk) t_c_in_c_out_dly <= t_c_in_c_out;
-
- adder32_artix7 add_t_c_in
- (
- .clk (clk),
- .ce (1'b1),
- .a (t_dly),
- .b (c_in_dly),
- .c_in (1'b0),
- .s (t_c_in_s),
- .c_out (t_c_in_c_out)
- );
-
- wire [63: 0] a_b;
-
- wire [31: 0] a_b_lsb = a_b[31: 0];
- wire [31: 0] a_b_msb = a_b[63:32];
-
- reg [31: 0] a_b_msb_dly;
-
- always @(posedge clk) a_b_msb_dly <= a_b_msb;
-
- multiplier32_artix7 mul_a_b
- (
- .clk (clk),
- .a (a),
- .b (b),
- .p (a_b)
- );
-
- wire [31: 0] add_p_s;
- wire add_p_c_out;
-
- reg [31: 0] add_p_s_dly;
-
- always @(posedge clk) add_p_s_dly <= add_p_s;
-
- assign p = add_p_s_dly;
-
- adder32_artix7 add_p
- (
- .clk (clk),
- .ce (1'b1),
- .a (a_b_lsb),
- .b (t_c_in_s),
- .c_in (1'b0),
- .s (add_p_s),
- .c_out (add_p_c_out)
- );
-
- adder32_artix7 add_c_out
- (
- .clk (clk),
- .ce (1'b1),
- .a (a_b_msb_dly),
- .b ({{31{1'b0}}, t_c_in_c_out_dly}),
- .c_in (add_p_c_out),
- .s (c_out),
- .c_out ()
- );
-
-endmodule
-
+//------------------------------------------------------------------------------
+
+module modexpa7_systolic_pe_artix7
+ (
+ input clk,
+ input [31: 0] a,
+ input [31: 0] b,
+ input [31: 0] t,
+ input [31: 0] c_in,
+ output [31: 0] p,
+ output [31: 0] c_out
+ );
+
+ reg [31: 0] t_dly;
+ reg [31: 0] c_in_dly;
+
+ always @(posedge clk) t_dly <= t;
+ always @(posedge clk) c_in_dly <= c_in;
+
+ wire [31: 0] t_c_in_s;
+ wire t_c_in_c_out;
+
+ reg t_c_in_c_out_dly;
+
+ always @(posedge clk) t_c_in_c_out_dly <= t_c_in_c_out;
+
+ modexpa7_adder32_artix7 add_t_c_in
+ (
+ .clk (clk),
+ .ce (1'b1),
+ .a (t_dly),
+ .b (c_in_dly),
+ .c_in (1'b0),
+ .s (t_c_in_s),
+ .c_out (t_c_in_c_out)
+ );
+
+ wire [63: 0] a_b;
+
+ wire [31: 0] a_b_lsb = a_b[31: 0];
+ wire [31: 0] a_b_msb = a_b[63:32];
+
+ reg [31: 0] a_b_msb_dly;
+
+ always @(posedge clk) a_b_msb_dly <= a_b_msb;
+
+ modexpa7_multiplier32_artix7 mul_a_b
+ (
+ .clk (clk),
+ .a (a),
+ .b (b),
+ .p (a_b)
+ );
+
+ wire [31: 0] add_p_s;
+ wire add_p_c_out;
+
+ reg [31: 0] add_p_s_dly;
+
+ always @(posedge clk) add_p_s_dly <= add_p_s;
+
+ assign p = add_p_s_dly;
+
+ modexpa7_adder32_artix7 add_p
+ (
+ .clk (clk),
+ .ce (1'b1),
+ .a (a_b_lsb),
+ .b (t_c_in_s),
+ .c_in (1'b0),
+ .s (add_p_s),
+ .c_out (add_p_c_out)
+ );
+
+ modexpa7_adder32_artix7 add_c_out
+ (
+ .clk (clk),
+ .ce (1'b1),
+ .a (a_b_msb_dly),
+ .b ({{31{1'b0}}, t_c_in_c_out_dly}),
+ .c_in (add_p_c_out),
+ .s (c_out),
+ .c_out ()
+ );
+
+endmodule
+
//------------------------------------------------------------------------------
// End-of-File
-//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/adder32_generic.v b/src/rtl/pe/generic/modexpa7_adder32_generic.v
similarity index 97%
rename from src/rtl/pe/generic/adder32_generic.v
rename to src/rtl/pe/generic/modexpa7_adder32_generic.v
index 10ecfa4..8ecd292 100644
--- a/src/rtl/pe/generic/adder32_generic.v
+++ b/src/rtl/pe/generic/modexpa7_adder32_generic.v
@@ -1,8 +1,8 @@
//------------------------------------------------------------------------------
//
-// adder32_generic.v
+// modexpa7_adder32_generic.v
// -----------------------------------------------------------------------------
-// Generic 32-bit adder w/ clock enable.
+// Generic 32-bit adder w/ clock enable.
//
// Authors: Pavel Shatov
//
@@ -34,36 +34,36 @@
// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
// POSSIBILITY OF SUCH DAMAGE.
//
-//------------------------------------------------------------------------------
-
-module adder32_generic
- (
- input clk, // clock
- input ce, // clock enable
- input [31: 0] a, // operand input
- input [31: 0] b, // operand input
- output [31: 0] s, // sum output
- input c_in, // carry input
- output c_out // carry output
- );
+//------------------------------------------------------------------------------
+
+module modexpa7_adder32_generic
+ (
+ input clk, // clock
+ input ce, // clock enable
+ input [31: 0] a, // operand input
+ input [31: 0] b, // operand input
+ output [31: 0] s, // sum output
+ input c_in, // carry input
+ output c_out // carry output
+ );
//
// Sum
//
- reg [32: 0] s_int;
-
- always @(posedge clk)
- if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
-
- //
- // Output
- //
- assign s = s_int[31:0];
- assign c_out = s_int[32];
-
-
-endmodule
-
+ reg [32: 0] s_int;
+
+ always @(posedge clk)
+ if (ce) s_int <= {1'b0, a} + {1'b0, b} + {{32{1'b0}}, c_in};
+
+ //
+ // Output
+ //
+ assign s = s_int[31:0];
+ assign c_out = s_int[32];
+
+
+endmodule
+
//------------------------------------------------------------------------------
// End-of-File
-//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/subtractor32_generic.v b/src/rtl/pe/generic/modexpa7_subtractor32_generic.v
similarity index 95%
rename from src/rtl/pe/generic/subtractor32_generic.v
rename to src/rtl/pe/generic/modexpa7_subtractor32_generic.v
index 3e78715..b805c10 100644
--- a/src/rtl/pe/generic/subtractor32_generic.v
+++ b/src/rtl/pe/generic/modexpa7_subtractor32_generic.v
@@ -1,71 +1,71 @@
-//------------------------------------------------------------------------------
-//
-// subtractor32_generic.v
-// -----------------------------------------------------------------------------
-// Generic 32-bit subtractor w/ clock enable.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2016-2017, NORDUnet A/S
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions are met:
-//
-// - Redistributions of source code must retain the above copyright notice,
-// this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright notice,
-// this list of conditions and the following disclaimer in the documentation
-// and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may be
-// used to endorse or promote products derived from this software without
-// specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-// POSSIBILITY OF SUCH DAMAGE.
-//
-//------------------------------------------------------------------------------
-
-module subtractor32_generic
- (
- input clk,
- input ce,
- input [31: 0] a,
- input [31: 0] b,
- output [31: 0] d,
- input b_in,
- output b_out
- );
-
-
+//------------------------------------------------------------------------------
+//
+// modexpa7_subtractor32_generic.v
+// -----------------------------------------------------------------------------
+// Generic 32-bit subtractor w/ clock enable.
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2016-2017, NORDUnet A/S
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions are met:
+//
+// - Redistributions of source code must retain the above copyright notice,
+// this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright notice,
+// this list of conditions and the following disclaimer in the documentation
+// and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may be
+// used to endorse or promote products derived from this software without
+// specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+// POSSIBILITY OF SUCH DAMAGE.
+//
+//------------------------------------------------------------------------------
+
+module modexpa7_subtractor32_generic
+ (
+ input clk,
+ input ce,
+ input [31: 0] a,
+ input [31: 0] b,
+ output [31: 0] d,
+ input b_in,
+ output b_out
+ );
+
+
//
// Difference
//
- reg [32: 0] d_int;
-
- always @(posedge clk)
- if (ce) d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in};
-
-
- //
- // Output
- //
- assign d = d_int[31:0];
- assign b_out = d_int[32];
-
-
-endmodule
-
-//------------------------------------------------------------------------------
-// End-of-File
-//------------------------------------------------------------------------------
+ reg [32: 0] d_int;
+
+ always @(posedge clk)
+ if (ce) d_int <= {1'b0, a} - {1'b0, b} - {{32{1'b0}}, b_in};
+
+
+ //
+ // Output
+ //
+ assign d = d_int[31:0];
+ assign b_out = d_int[32];
+
+
+endmodule
+
+//------------------------------------------------------------------------------
+// End-of-File
+//------------------------------------------------------------------------------
diff --git a/src/rtl/pe/generic/systolic_pe_generic.v b/src/rtl/pe/generic/modexpa7_systolic_pe_generic.v
similarity index 95%
rename from src/rtl/pe/generic/systolic_pe_generic.v
rename to src/rtl/pe/generic/modexpa7_systolic_pe_generic.v
index 6c98f44..389b1f9 100644
--- a/src/rtl/pe/generic/systolic_pe_generic.v
+++ b/src/rtl/pe/generic/modexpa7_systolic_pe_generic.v
@@ -1,85 +1,85 @@
-//======================================================================
-//
-// systolic_pe_generic.v
-// -----------------------------------------------------------------------------
-// Generic low-level systolic array processing element.
-//
-// Authors: Pavel Shatov
-//
-// Copyright (c) 2017, NORDUnet A/S All rights reserved.
-//
-// Redistribution and use in source and binary forms, with or without
-// modification, are permitted provided that the following conditions
-// are met:
-// - Redistributions of source code must retain the above copyright
-// notice, this list of conditions and the following disclaimer.
-//
-// - Redistributions in binary form must reproduce the above copyright
-// notice, this list of conditions and the following disclaimer in the
-// documentation and/or other materials provided with the distribution.
-//
-// - Neither the name of the NORDUnet nor the names of its contributors may
-// be used to endorse or promote products derived from this software
-// without specific prior written permission.
-//
-// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
-// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
-// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
-// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
-// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
-// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
-// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
-// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
-// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-//
-//======================================================================
-
-module systolic_pe_generic
- (
- input clk,
- input [31: 0] a,
- input [31: 0] b,
- input [31: 0] t,
- input [31: 0] c_in,
- output [31: 0] p,
- output [31: 0] c_out
- );
-
- //
- // Customizable Latency
- //
- parameter LATENCY = 4;
-
- //
- // Delay Line
- //
- reg [63: 0] abct[1:LATENCY];
-
- //
- // Outputs
- //
- assign p = abct[LATENCY][31: 0];
- assign c_out = abct[LATENCY][63:32];
-
- //
- // Sub-products
- //
- wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b};
- wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t};
-
- //
- // Delay
- //
- integer i;
- always @(posedge clk)
- //
- for (i=1; i<=LATENCY; i=i+1)
- abct[i] <= (i == 1) ? ab + ct : abct[i-1];
-
-endmodule
-
-//======================================================================
-// End of file
-//======================================================================
+//======================================================================
+//
+// modexpa7_systolic_pe_generic.v
+// -----------------------------------------------------------------------------
+// Generic low-level systolic array processing element.
+//
+// Authors: Pavel Shatov
+//
+// Copyright (c) 2017, NORDUnet A/S All rights reserved.
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+// - Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// - Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the distribution.
+//
+// - Neither the name of the NORDUnet nor the names of its contributors may
+// be used to endorse or promote products derived from this software
+// without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
+// IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
+// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
+// PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED
+// TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
+// PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
+// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
+// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+//======================================================================
+
+module modexpa7_systolic_pe_generic
+ (
+ input clk,
+ input [31: 0] a,
+ input [31: 0] b,
+ input [31: 0] t,
+ input [31: 0] c_in,
+ output [31: 0] p,
+ output [31: 0] c_out
+ );
+
+ //
+ // Customizable Latency
+ //
+ parameter LATENCY = 4;
+
+ //
+ // Delay Line
+ //
+ reg [63: 0] abct[1:LATENCY];
+
+ //
+ // Outputs
+ //
+ assign p = abct[LATENCY][31: 0];
+ assign c_out = abct[LATENCY][63:32];
+
+ //
+ // Sub-products
+ //
+ wire [63: 0] ab = {{32{1'b0}}, a} * {{32{1'b0}}, b};
+ wire [63: 0] ct = {{32{1'b0}}, c_in} + {{32{1'b0}}, t};
+
+ //
+ // Delay
+ //
+ integer i;
+ always @(posedge clk)
+ //
+ for (i=1; i<=LATENCY; i=i+1)
+ abct[i] <= (i == 1) ? ab + ct : abct[i-1];
+
+endmodule
+
+//======================================================================
+// End of file
+//======================================================================
diff --git a/src/rtl/pe/modexpa7_primitive_switch.v b/src/rtl/pe/modexpa7_primitive_switch.v
index 3551d7a..fa958ec 100644
--- a/src/rtl/pe/modexpa7_primitive_switch.v
+++ b/src/rtl/pe/modexpa7_primitive_switch.v
@@ -2,15 +2,15 @@
`ifdef USE_VENDOR_PRIMITIVES
-`define ADDER32_PRIMITIVE adder32_artix7
-`define SUBTRACTOR32_PRIMITIVE subtractor32_artix7
-`define SYSTOLIC_PE_PRIMITIVE systolic_pe_artix7
+`define ADDER32_PRIMITIVE modexpa7_adder32_artix7
+`define SUBTRACTOR32_PRIMITIVE modexpa7_subtractor32_artix7
+`define SYSTOLIC_PE_PRIMITIVE modexpa7_systolic_pe_artix7
`else
-`define ADDER32_PRIMITIVE adder32_generic
-`define SUBTRACTOR32_PRIMITIVE subtractor32_generic
-`define SYSTOLIC_PE_PRIMITIVE systolic_pe_generic
+`define ADDER32_PRIMITIVE modexpa7_adder32_generic
+`define SUBTRACTOR32_PRIMITIVE modexpa7_subtractor32_generic
+`define SYSTOLIC_PE_PRIMITIVE modexpa7_systolic_pe_generic
`endif
--
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