March 2014 Archives by subject

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Starting: Thu Mar 13 13:51:11 UTC 2014
Ending: Tue Mar 18 08:14:46 UTC 2014
Messages: 66

• [Cryptech-Commits] [core/coretest] 01/01: Adding license and readme file.   git at cryptech.is
• [Cryptech-Commits] [core/coretest] 01/01: Adding makefile to buld and run coretest simulation.   git at cryptech.is
• [Cryptech-Commits] [core/coretest] 01/01: Adding source files for coretest.   git at cryptech.is
• [Cryptech-Commits] [core/coretest] branch master created (now 0406147)   git at cryptech.is
• [Cryptech-Commits] [core/coretest] branch master updated (0406147 -> de1ba16)   git at cryptech.is
• [Cryptech-Commits] [core/coretest] branch master updated (de1ba16 -> 55fbc54)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/01: Adding bitstream file for coretest_hashes on the TerasIC C5G board.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/01: Adding Makefile to build the coretest_hashes subsystem.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/01: Adding project, assignment and clock setup files for Quartus and the TerasIC C5G board.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/01: Adding test program that checks the SHA-1 and SHA-256 cores and do single block hashing.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/01: Updating address for uart to 8 bits which should be the default.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 01/02: Adding readme and license for the coretest_hashes subsystem.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] 02/02: Adding RTL to build the coretest_hashes subsystem with SHA-1 and SHA-256 cores.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master created (now 6f6ab17)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master updated (2608109 -> fca501d)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master updated (6f6ab17 -> d9fb29d)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master updated (6ff77cf -> 2608109)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master updated (9a275f8 -> 6ff77cf)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_hashes] branch master updated (d9fb29d -> 9a275f8)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding a prebuilt FPGA configuration file for the TerasIC C5G board.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding clock define.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding license and readme file for the coretest_test_core subsystem.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding Makefile for building and running simulations.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding sw to run tests on a FPGA device connected to the FPGA board via a serial port.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding symbolic name and comment to highlight the serial port device.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding testbench for the coretest_test_core subsystem.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] 01/01: Adding the RTL that builds the subsystem.   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master created (now 96ef23f)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (0e51a3e -> de1eabf)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (6551944 -> ddc31ff)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (96ef23f -> 0e51a3e)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (ddc31ff -> f70c6f8)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (de1eabf -> 6551944)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (f70c6f8 -> ffc0246)   git at cryptech.is
• [Cryptech-Commits] [core/coretest_test_core] branch master updated (ffc0246 -> 497c12c)   git at cryptech.is
• [Cryptech-Commits] [core/sha1] 01/01: Added wait to allow the ready flag to be dropped with resettable flags. Fixed name of clock delay parameter.   git at cryptech.is
• [Cryptech-Commits] [core/sha1] 01/01: Removed redundant flag reset wires.   git at cryptech.is
• [Cryptech-Commits] [core/sha1] 01/01: Updating interface. Addding self resetting control regs. Fixing missing input port declaration that caused errors during simulation in ModelSim.   git at cryptech.is
• [Cryptech-Commits] [core/sha1] branch master updated (5b7e7a8 -> 6131547)   git at cryptech.is
• [Cryptech-Commits] [core/sha1] branch master updated (6131547 -> af4e880)   git at cryptech.is
• [Cryptech-Commits] [core/sha1] branch master updated (af4e880 -> ed0edb4)   git at cryptech.is
• [Cryptech-Commits] [core/sha256] 01/01: (1) Updated interface to new std. (2) Added missing input designation in tasks. Now simumaltion with ModelSim works.   git at cryptech.is
• [Cryptech-Commits] [core/sha256] 01/01: Adding self resetting init and next flags. Updating TBs to not reset the flags. Fixing clock parameter naming.   git at cryptech.is
• [Cryptech-Commits] [core/sha256] 01/01: Removed redundant flag reset wires.   git at cryptech.is
• [Cryptech-Commits] [core/sha256] branch master updated (52c2f0b -> 6e8e124)   git at cryptech.is
• [Cryptech-Commits] [core/sha256] branch master updated (6e8e124 -> c33d1df)   git at cryptech.is
• [Cryptech-Commits] [core/sha256] branch master updated (c33d1df -> 7725609)   git at cryptech.is
• [Cryptech-Commits] [core/test_core] 01/02: Adding license and readme for the test_core.   git at cryptech.is
• [Cryptech-Commits] [core/test_core] 02/02: Adding RTL for the test_core.   git at cryptech.is
• [Cryptech-Commits] [core/test_core] branch master created (now 240a517)   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/01: Adding license and readme files for the uart.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/01: Adding makefile to build and run uart simulations.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/01: Adding Python program to test the uart.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/01: Adding size constraints to constant definitions to remove synthesis warnings.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/01: Changing from blocking to correct, non-blocking assignments in reg update.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 01/02: Adding RTL files for the uart.   git at cryptech.is
• [Cryptech-Commits] [core/uart] 02/02: Adding testbench for the uart.   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master created (now 75b908f)   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master updated (355977f -> 6169f43)   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master updated (6169f43 -> b250c13)   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master updated (75b908f -> 9fd0e15)   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master updated (9fd0e15 -> 355977f)   git at cryptech.is
• [Cryptech-Commits] [core/uart] branch master updated (b250c13 -> 5d15271)   git at cryptech.is
• [Cryptech-Commits] [doc/presentations] 01/02: Adding the HW status preso from the meeting 2014-03-10.   git at cryptech.is
• [Cryptech-Commits] [doc/presentations] 02/02: Adding the TRNG ideas preso.   git at cryptech.is
• [Cryptech-Commits] [doc/presentations] branch master created (now b6cb367)   git at cryptech.is

Last message date: Tue Mar 18 08:14:46 UTC 2014
Archived on: Tue Mar 18 08:14:48 UTC 2014

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