[Cryptech-Commits] [core/coretest_test_core] 01/01: Adding clock define.

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joachim at secworks.se pushed a commit to branch master
in repository core/coretest_test_core.

commit 497c12ce2ff4151f1c711255b193cc9b6fe7740d
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Sun Mar 16 21:28:42 2014 +0100

    Adding clock define.
---
 .../quartus/terasic_c5g/coretest_test_core.sdc     | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

diff --git a/toolruns/quartus/terasic_c5g/coretest_test_core.sdc b/toolruns/quartus/terasic_c5g/coretest_test_core.sdc
new file mode 100644
index 0000000..93e1282
--- /dev/null
+++ b/toolruns/quartus/terasic_c5g/coretest_test_core.sdc
@@ -0,0 +1,40 @@
+#************************************************************
+# THIS IS A WIZARD-GENERATED FILE.                           
+#
+# Version 13.1.2 Build 173 01/15/2014 SJ Web Edition
+#
+#************************************************************
+
+# Copyright (C) 1991-2014 Altera Corporation
+# Your use of Altera Corporation's design tools, logic functions 
+# and other software and tools, and its AMPP partner logic 
+# functions, and any output files from any of the foregoing 
+# (including device programming or simulation files), and any 
+# associated documentation or information are expressly subject 
+# to the terms and conditions of the Altera Program License 
+# Subscription Agreement, Altera MegaCore Function License 
+# Agreement, or other applicable license agreement, including, 
+# without limitation, that your use is for the sole purpose of 
+# programming logic devices manufactured by Altera and sold by 
+# Altera or its authorized distributors.  Please refer to the 
+# applicable agreement for further details.
+
+
+
+# Clock constraints
+
+create_clock -name "clk" -period 20.000ns [get_ports {clk}]
+
+
+# Automatically constrain PLL and other generated clocks
+derive_pll_clocks -create_base_clocks
+
+# Automatically calculate clock uncertainty to jitter and other effects.
+derive_clock_uncertainty
+
+# tsu/th constraints
+
+# tco constraints
+
+# tpd constraints
+