[Cryptech-Commits] [core/uart] 01/01: Adding makefile to build and run uart simulations.

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joachim at secworks.se pushed a commit to branch master
in repository core/uart.

commit 6169f43f900da676a3c177029b5a8a4e1baa2a7a
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Mar 13 15:43:49 2014 +0100

    Adding makefile to build and run uart simulations.
---
 toolruns/Makefile | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 70 insertions(+)

diff --git a/toolruns/Makefile b/toolruns/Makefile
new file mode 100755
index 0000000..f088e86
--- /dev/null
+++ b/toolruns/Makefile
@@ -0,0 +1,70 @@
+#===================================================================
+#
+# Makefile
+# --------
+# Makefile for building uart core simulations.
+#
+#
+# Author: Joachim Strombergson
+# Copyright (c) 2014, SUNET
+# All rights reserved.
+# 
+# Redistribution and use in source and binary forms, with or 
+# without modification, are permitted provided that the following 
+# conditions are met: 
+# 
+# 1. Redistributions of source code must retain the above copyright 
+#    notice, this list of conditions and the following disclaimer. 
+# 
+# 2. Redistributions in binary form must reproduce the above copyright 
+#    notice, this list of conditions and the following disclaimer in 
+#    the documentation and/or other materials provided with the 
+#    distribution. 
+# 
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE 
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, 
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER 
+# CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 
+# STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 
+# ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+#
+#===================================================================
+
+UART_SRC=../src/rtl/uart.v ../src/rtl/uart_core.v
+UART_TB_SRC=../src/tb/tb_uart.v
+
+CC=iverilog
+
+
+all: uart
+
+
+uart:  $(UART_TB_SRC) $(UART_SRC)
+	$(CC) -o uart.sim $(UART_TB_SRC) $(UART_SRC)
+
+sim-uart: uart.sim
+	./uart.sim
+
+
+clean:
+	rm -f uart.sim
+
+
+help:
+	@echo "Supported targets:"
+	@echo "------------------"
+	@echo "all:      Build all simulation targets."
+	@echo "uart:     Build the uart simulation target."
+	@echo "sim-uart: Run the uart simulation."
+	@echo "clean:    Delete all built files."
+
+#===================================================================
+# EOF Makefile
+#===================================================================
+