[Cryptech-Commits] [core/uart] 01/01: Adding license and readme files for the uart.

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joachim at secworks.se pushed a commit to branch master
in repository core/uart.

commit 75b908ff8480edd67f342999f7a8dcb834702fc1
Author: Joachim Strömbergson <joachim at secworks.se>
Date:   Thu Mar 13 15:39:06 2014 +0100

    Adding license and readme files for the uart.
---
 LICENSE   | 24 ++++++++++++++++++++++++
 README.md |  9 +++++++++
 2 files changed, 33 insertions(+)

diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..0fb159c
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,24 @@
+Author: Joachim Strömbergson
+Copyright (c) 2014, SUNET
+All rights reserved.
+
+Redistribution and use in source and binary forms, with or without modification,
+are permitted provided that the following conditions are met:
+
+* Redistributions of source code must retain the above copyright notice, this
+  list of conditions and the following disclaimer.
+
+* Redistributions in binary form must reproduce the above copyright notice, this
+  list of conditions and the following disclaimer in the documentation and/or
+  other materials provided with the distribution.
+
+THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
diff --git a/README.md b/README.md
new file mode 100644
index 0000000..5361cd0
--- /dev/null
+++ b/README.md
@@ -0,0 +1,9 @@
+uart
+====
+
+A Universal asynchronous receiver/transmitter (UART) implemented in Verilog.
+
+This UART used to be in coretest, but has been moved out as a separate
+project.
+
+