July 2017 Archives by date

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Starting: Sat Jul 1 15:48:19 UTC 2017
Ending: Thu Jul 27 07:44:41 UTC 2017
Messages: 39

• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Added 512-bit test vector Cleaned up Verilog a bit   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated (a69a530 -> a62861f)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/02: Cleaned up Verilog sources   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/02: Added generic/vendor-specific primitive selector for simulation.   git at cryptech.is
• [Cryptech-Commits] [user/sra/openssl-engine] branch master updated: TLS example.   git at cryptech.is
• [Cryptech-Commits] [user/sra/openssl-engine] branch master updated: Cleanup.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated (e91ce07 -> 9e56430)   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] 01/03: Triple multiplier turns out to be an overkill in Verilog, started turning systolic multiplication into a separate procedure.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] 02/03: Turned systolic multiplication into a separate routine.   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] 03/03: Minor update, there's no need to update Aj inside of systolic loop.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated (a62861f -> 71b7529)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/04: Started porting generic multiplier to Xilinx primitives.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/04: Fixing generic/vendor primitive switching...   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 03/04: Fixed generic/vendor low-level primitives switch.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 04/04: * made separate file for low-level settings * turned crazy triple multiplier array into one array with input mux   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Systolic multiplier simplified a bit: * passes testbench tests again * this time synthesizes fine (without major issues)   git at cryptech.is
• [Cryptech-Commits] [user/shatov/modexp_fpga_model] branch master updated: Changes to the model: * Follow what Verilog does more closely: FPGA can't do PP = P * P, because it can't read from two different block mem P locations at the same time, we have to do P1 = P2 = P, PP = P1 * P2 * Updated the test vector script to format additional quantities to help debug Verilog exponentiation module * Added the trick suggested by Bernd Paysan to help better conceal whether we're discarding multiplication result when the current exponent bit is not set   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Started adding exponentiator module w/ testbench.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated (d887154 -> c3d75e5)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/03: Finished modular exponentiation module: * works in simulator * passes synthesis without major issues   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/03: Added pre-multiplication step. Added 512-bit testbench.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 03/03: Fixed bug in systolic multiplier (swapped indices), it only worked because the testbench set both NUM_SYSTOLIC_CYCLES = 4 and SYSTOLIC_ARRAY_LENGTH = 4. Now should work with any array power, not only 2.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated (c3d75e5 -> c6ea5d8)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/02: Converted pe_c_out_mem two-dimensional array into a FIFO.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/02: Force inference of distributed memory for the simple FIFO used to store carries.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated (c6ea5d8 -> b33f595)   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 01/02: Converted pe_t array into a FIFO too. No more nasty messages during synthesis. Still needs a tiny bit of cleanup.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] 02/02: Wrote top-level module. 4096-bit core with 16-tap systolic array synthesizes just fine: 10% slices 8% block memory 33% DSPs   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Started adding top-level wrapper.   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] branch master updated (98a7a91 -> 19f9279)   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] 01/04: Key generation timing.   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] 02/04: Fencepost error (1-based counting using xrange(), sigh).   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] 03/04: Use ModExp fast mode for Miller-Rabin tests.   git at cryptech.is
• [Cryptech-Commits] [sw/libhal] 04/04: Split compile-time control of RSA ModExp.   git at cryptech.is
• [Cryptech-Commits] [releng/alpha] branch master updated: Pull in RSA key generation changes.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Trying to fix the bug during calculation of SN in systolic multiplier.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Wide operand loader needs simplification...   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Work in progress.   git at cryptech.is
• [Cryptech-Commits] [core/math/modexpa7] branch systolic updated: Work in progress.   git at cryptech.is

Last message date: Thu Jul 27 07:44:41 UTC 2017
Archived on: Thu Jul 27 07:44:44 UTC 2017

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