[Cryptech-Commits] [core/math/modexpa7] branch systolic updated (a69a530 -> a62861f)

[git at cryptech.is]

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meisterpaul1 at yandex.ru pushed a change to branch systolic
in repository core/math/modexpa7.

    from a69a530  Added 512-bit test vector Cleaned up Verilog a bit
     new 73fd793  Cleaned up Verilog sources
     new a62861f  Added generic/vendor-specific primitive selector for simulation.

The 2 revisions listed above as "new" are entirely new to this
repository and will be described in separate emails.  The revisions
listed as "add" were already present in the repository and have only
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Summary of changes:
 src/rtl/modexpa7_factor.v                 | 187 ++++++++++++++++++++----------
 src/rtl/modexpa7_n_coeff.v                |   3 +-
 src/rtl/pe/artix7/adder32_artix7.v        |  97 ++++++++++++++++
 src/rtl/pe/artix7/dsp48e1_wrapper.v       | 159 +++++++++++++++++++++++++
 src/rtl/pe/artix7/subtractor32_artix7.v   |  95 +++++++++++++++
 src/rtl/pe/generic/adder32_generic.v      |  69 +++++++++++
 src/rtl/pe/generic/subtractor32_generic.v |  71 ++++++++++++
 src/rtl/pe/modexpa7_pe_add.v              |  27 +++--
 src/rtl/pe/modexpa7_pe_settings.v         |  13 +++
 src/rtl/pe/modexpa7_pe_sub.v              |  27 +++--
 src/tb/tb_factor.v                        |   4 +-
 src/tb/tb_systolic_multiplier.v           |   2 +-
 12 files changed, 675 insertions(+), 79 deletions(-)
 create mode 100644 src/rtl/pe/artix7/adder32_artix7.v
 create mode 100644 src/rtl/pe/artix7/dsp48e1_wrapper.v
 create mode 100644 src/rtl/pe/artix7/subtractor32_artix7.v
 create mode 100644 src/rtl/pe/generic/adder32_generic.v
 create mode 100644 src/rtl/pe/generic/subtractor32_generic.v
 create mode 100644 src/rtl/pe/modexpa7_pe_settings.v