[Cryptech Tech] keystore flash performance

Peter Stuge peter at stuge.se
Thu Feb 23 00:57:36 UTC 2017

Paul Selkirk wrote:
> I'm not an expert, and I haven't fully re-read the 84 page data sheet
> for the chip, but looking at the timing diagrams, there doesn't seem to
> be any need for a delay between transmitting the command and receiving
> the result, or for a delay before de-selecting the chip,

Yeah, only write operations should need a bit of time. And there I
strongly recommend polling the flash instead of waiting a fixed time,
if possible.

> The sequence of events is like this:
> send WRITE_ENABLE, delay 1ms

1 ms also seems very long here.

> Erase shows more modest gains, because each operation takes a lot
> longer,

Here you can gain performance by always using the largest erase
operation possible. Some chips have multiple page sizes with
different erase operations.


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