[Cryptech Tech] keystore flash performance

[Paul Selkirk]

I inadvertently replied just to Peter. Sending to the list to archive
the conversation.

-------- Forwarded Message --------
Subject: Re: [Cryptech Tech] keystore flash performance
Date: Thu, 23 Feb 2017 13:51:25 -0500
From: Paul Selkirk <paul at psgd.org>
To: Peter Stuge <peter at stuge.se>

On 02/22/2017 07:57 PM, Peter Stuge wrote:
> Yeah, only write operations should need a bit of time. And there I
> strongly recommend polling the flash instead of waiting a fixed time,
> if possible.

Yep, that's what we do now.

> Here you can gain performance by always using the largest erase
> operation possible. Some chips have multiple page sizes with
> different erase operations.

For the CLI command 'keystore erase', we now use the "bulk erase"
operation, which erases the whole 16MB chip in 46 sec. When uploading a
new FPGA bitstream, we erase one 64KB sector at a time, because the
current bitstream is only 4.5MB, and inserting a 260ms erase operation
is hardly noticeable. For keystore operations, we erase one 4KB
subsector at a time, because that's the size of the key storage block.

				paul