[Cryptech Tech] keystore flash performance
fredrik at thulin.net
Tue Feb 21 08:54:59 UTC 2017
On måndag 20 februari 2017 kl. 18:14:20 CET Paul Selkirk wrote:
> In the course of reviewing Rob's new keystore architecture (ksng
> branches in the libhal, pkcs11, and stm32 repos), I've been looking at
> performance of the SPI flash chip. In short, most of the poor
> performance is self-inflicted.
> As originally coded, there were 1ms delays after every SPI operation
> (both transmit and receive), and an additional 10ms delay in the
> _wait_while_wip() loop. I was able to significantly speed up flash
> operations just by removing these delays, with no loss of stability or
> I'm not an expert, and I haven't fully re-read the 84 page data sheet
> for the chip, but looking at the timing diagrams, there doesn't seem to
> be any need for a delay between transmitting the command and receiving
> the result, or for a delay before de-selecting the chip, especially
> since the low-level SPI code has its own timeout mechanism. Maybe
> Fredrik can comment?
Good find, and nice work. How much is the bottom line gains for something like
a DNSSEC signer?
I'll defer commenting on the need for delays to Pavel who wrote the original
code for communicating with the N25Q128.
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