[Cryptech Tech] debug output from cores?

[Joachim Strömbergson]

-----BEGIN PGP SIGNED MESSAGE-----
Hash: SHA256

Aloha!

Here is another nice interface topic. ;-)

The rng cores (avalanche_entropy, rosc_entropy, trng) all sports a debug
port. The purpose of that port is/was to be able to get some data out
from the FPGA to see that the entropy sources and trng is alive even
though the CPU might be missing.

But do we really need these ports still?

Extracting data and sending it to pins on the FPGA (to drive LEDs) can
be achieved with an internal bus master. Or by SW.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
========================================================================
-----BEGIN PGP SIGNATURE-----
Comment: GPGTools - http://gpgtools.org
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org/

iQIcBAEBCAAGBQJWEiezAAoJEF3cfFQkIuyN9hwQALGWahjePJIrnEF2KnVlrWx4
3cbd4jN9NiQ9SN2E+Vhqf6Zx7UQIMTn4MlPRBb1ncPEh+IvS1+5epl+Zw1manym+
fzWXtXFzc+VJlFouYlNaidpQLpypO5RcTRusWbOxSjL6W+h+fvrxjgJJoyDHp3es
rgx0GCwRj9SNNSmDN+zNMwXv54RemhlDUhxsh8eUwtEwDQ8Lvj5jYVlefSBrfx5d
oXHUw97B8vQNGpU5zgXOWo9uM6KZZ0G6pnUHsxMhe8KjDaVZODe43zRXY6U0RBOC
HKNyKcFOhV6B7w0kTzdoj/nlEJ89x1X119jO7DCMFBMA8KQp36C/4iT5aUt30/Jc
1mzBTiG4hf0fHa0x5fH9+XR2Ns/hX4z7/ssnFP61AI1PQfgn7ejkT/Cnb6RCoil/
Um4G+38nTu/Lk4KF6XkvL6Eukr+O/Mxo0YF9ejjrhcHOStRkxRfmaMVgBcCrWQYX
Q6rUoApmCe3zrS3SgWRJ8QUVBvpJfMTT4E3AB19Td59u0NrGQD7FGZTMEh2b+rOr
AaUCA6sqaSlYTUEwiFWKaRr10KTdJe/WgeKiEiMxS2bVgmgWbVIwvQOF88Gu9ZO8
hnnSMB6gianUqzJ/NRItDcTGqmSTGdKVpJ+WMpw76ZvIDTpgn1elNpsxlftisU9E
cYPsK/FzoytKuQF4cNLy
=3XdL
-----END PGP SIGNATURE-----