[Cryptech Tech] Updated novena noise board

[Jacob]

On 6/2/2015 12:02 PM, Fredrik Thulin wrote:
>
>>
>> Some issues:
>>
>> 1. Comps' Ref Des were not generated (the Silk Gerber looks like your 3D
>> picture).
>
> I'm having slight difficulties decoding your abbreviated naming here, but I
> guess it is Components Reference Descriptions and refer to the tName layer
> with texts such as C1, R6, U1?
>
> I left it out because of aesthetics - given the audience for these boards, I'm
> thinking they will be manufactured once and viewed many many times, by many
> people. IMO, the board looks much better without the tName information and,
> sadly for prospective manufacturers, with the suboptimal placements of the top
> layer fiducials.
>
> I've attached two renderings of the board for comparison.

Apologies for the abbreviated naming. Comp Ref Des stands for Component 
Reference Designator - the U1, C10 etc.

Almost all boards have them. They are used by Assembly House internal 
management: QA, Assemblers etc. They are also used by the electronic 
designers when checking board operation and debugging in the lab - 
correlating schematic points to the physical board for probing.
They are also used in QA and field support - when a customer reports 
that U1 starts to smoke, how could he relay that info otherwise?

Not only that, but many designers require that connectors or big 
components like MCU or FPGA to carry silk markers every 5th/10th pin or 
so to aid in probe placement in the lab.

I have never heard that there is an aesthetic issue with Ref Des 
marking, but this maybe because having Ref Des on board is so ingrained 
into the electronic designers and layout engineers psyche.

>
>> 2. Some vias are covered with solder mask, some aren't. Not critical though.
>
> Yes, spotted that after I sent the mail yesterday and fixed it. I changed the
> annular ring size to try and avoid bad boards due to imprecise drilling, and
> apparently had to change another setting to avoid the tenting of vias. Maybe
> tenting them all would have looked even nicer, but I wanted at least the
> stitching vias around the shielding cabinet base to be unmasked to really get
> solder in there.

In dense boards we normally cover vias with Solder Mask (SM) to avoid a 
possible short if adjacent to pads. In dev boards, sometimes engineers 
want uncovered via so they could insert wires into them to reroute some 
traces or short some nets. If you wish you could have mixed types but 
there should be a reason for one kind over the other.

>
> Speaking of the shielding cabinet - for now I've planned to mount those
> manually after any reflow soldering of components. The reason is that the
> shield absorbs a lot of heat, so at least for my amateurish reflow soldering
> at home I had to raise the temperature of the profile by about 10 degrees C to
> get correct soldering of the components inside the shielding cabinet, and even
> then the soldering joints for the cabinet did not look that good to me.
>
> If we were planning for mass production of these boards, I'm sure it would be
> better to work out a real temperature profile with a real assembly house, but
> I think manual soldering is the best option for now.

I concur - hand soldering the shield after the reflow cycle. With IR 
reflow oven it is almost impossible to have a good reflow of comps 
inside a shield, while at the same time avoiding damaging other temp 
sensitive comps on the board.


Note: make sure that the shield has a small recess over the 3 traces 
coming out of the noisy region. If not, there is a danger of the 
shield's metal edge scrubbing and shorting them out.

>> 4. This is major: the file .GTO appears to be comp outline silk. It is
>> not a good one though - it covers the comps pads.
>
> Thanks. Removed the tDocu layer from the silk screen generation. I've been
> reading that board houses just remove printing from where there are pads, but
> that's not a reason to not make it right.
>
> On the attached illustrations, I unchecked the "Top solder paste" box so it's
> clearly shown on e.g. the top right four capacitors that the silk screen is
> not any longer on the pads.
>

Good. Please note that Ref Des should be outside the component's 
outline, so it is readable after the board is assembled.
Also note the misplaced SJ1 - after assembly it will be shown only as J1 
..   You can reduce Ref Des font size, or rotate 90 degrees, if space is 
tight.

Vendors usually clear silk off pads, but sometimes they miss. You need 
to know your board fab house and his attention to details.


Jacob