[Cryptech Tech] Updated novena noise board

[Fredrik Thulin]

On Tuesday, June 02, 2015 01:03:16 AM Jacob wrote:
> On 6/1/2015 11:36 PM, Fredrik Thulin wrote:
> > I have now updated the rev03 board with almost all the suggestions I've
> > gotten from my kind reviewers Jacob, Peter, Pavel and bunnie.
> > 
> > I've also hopefully sorted out how to generate Gerbers properly - at least
> > the attached Gerbers loads just fine with the nifty online 3D viewer at
> > http://mayhewlabs.com/3dpcb (try it, really cool!) and online renderings
> > from two PCB houses look OK, and it looks good (to me) with the 'gerbv'
> > Linux viewer.
> 
> Fredrik, I took a quick look at the latest files.
> Traces are now looking good. Also the Solder Mask opening around the
> connector's pins.

Thanks, great.

> Fiducials are kind of OK. It would be better to increase the triangle
> base (see attached pic) and also to have a clearance, including Solder
> Mask clearance, on the full 80 mil diameter.

Ok. See response to 1 below.

> 
> Some issues:
> 
> 1. Comps' Ref Des were not generated (the Silk Gerber looks like your 3D
> picture).

I'm having slight difficulties decoding your abbreviated naming here, but I 
guess it is Components Reference Descriptions and refer to the tName layer 
with texts such as C1, R6, U1?

I left it out because of aesthetics - given the audience for these boards, I'm 
thinking they will be manufactured once and viewed many many times, by many 
people. IMO, the board looks much better without the tName information and, 
sadly for prospective manufacturers, with the suboptimal placements of the top 
layer fiducials.

I've attached two renderings of the board for comparison.

> 2. Some vias are covered with solder mask, some aren't. Not critical though.

Yes, spotted that after I sent the mail yesterday and fixed it. I changed the 
annular ring size to try and avoid bad boards due to imprecise drilling, and 
apparently had to change another setting to avoid the tenting of vias. Maybe 
tenting them all would have looked even nicer, but I wanted at least the 
stitching vias around the shielding cabinet base to be unmasked to really get 
solder in there.

Speaking of the shielding cabinet - for now I've planned to mount those 
manually after any reflow soldering of components. The reason is that the 
shield absorbs a lot of heat, so at least for my amateurish reflow soldering 
at home I had to raise the temperature of the profile by about 10 degrees C to 
get correct soldering of the components inside the shielding cabinet, and even 
then the soldering joints for the cabinet did not look that good to me.

If we were planning for mass production of these boards, I'm sure it would be 
better to work out a real temperature profile with a real assembly house, but 
I think manual soldering is the best option for now.

> 3.There is a via on the left mechanical pad of the connector. Why is it
> there?

I moved it to below the mechanical pad. Thanks for pointing it out - I guess 
it would be problematic for reflow soldering of the bottom side connector. 
Didn't think of that since I've only been soldering those by hand =).

> 4. This is major: the file .GTO appears to be comp outline silk. It is
> not a good one though - it covers the comps pads.

Thanks. Removed the tDocu layer from the silk screen generation. I've been 
reading that board houses just remove printing from where there are pads, but 
that's not a reason to not make it right.

On the attached illustrations, I unchecked the "Top solder paste" box so it's 
clearly shown on e.g. the top right four capacitors that the silk screen is 
not any longer on the pads.

/Fredrik
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