[Cryptech Tech] Test build of the Cryptech rosc entropy source

[Joachim Strömbergson]

Aloha!

I've added a test design for the rosc entropy source that instantiates a
single oscillator in a way to allow analysis of how the oscillator is
mapped onto the structures in a given FPGA technology. (It sounds
fancier that it is ;-)

I've also tested a couple of versions of the oscillator where the adder
logic (which forms the combinatorial delay at the heart of the
oscillator) is implemented with 1, 2 or 3 bit wide operands respectively.

For Xilinx Spartan-6 one can see that the feedback path from carry out
to carry in is always connected outside the FPGA logic block (the
slice). This means that the intrinsic delay and thus the frequency of
the oscillator is affected by routing for a given oscillator. This also
means that the oscillators in separate builds of the same design for the
same type of FPGA device may vary since placement can vary based on P&R
seed.

For operands that are one or two bits, the adder is implemented in a
single slice. For three bit operands and more, the adder is split onto
more than one slice. This introduces more routing effects on the
oscillator frequency.

I've attached FPGA floorplan images that shows the feedback path for
designs with 1, 2 and 3 bit operands. (The feedback path is the red path).

-- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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