[Cryptech Tech] Test build of the Cryptech rosc entropy source

[Павел Шатов]

On 13.04.2015 16:36, Joachim Strömbergson wrote:
 >
> For Xilinx Spartan-6 one can see that the feedback path from carry out
> to carry in is always connected outside the FPGA logic block (the
> slice). This means that the intrinsic delay and thus the frequency of
> the oscillator is affected by routing for a given oscillator. This also
> means that the oscillators in separate builds of the same design for the
> same type of FPGA device may vary since placement can vary based on P&R
> seed.
>
> For operands that are one or two bits, the adder is implemented in a
> single slice. For three bit operands and more, the adder is split onto
> more than one slice. This introduces more routing effects on the
> oscillator frequency.

Well, you can use LOC constraint to enforce placement. Let's lock 
location of LED blink counter in novena_base design, for example.

First of all, we need to find out where ISE initially placed our 
register. You can use FPGA Editor to find out target slice coordinates 
(fpga_site.png) Use filter to quickly find target register, double-click 
it and then click that red box on the left to display its actual 
location in the status bar. In my case it is "SLICE_X49Y107".

Then we need to find out, how our register was named during synthesis. 
Click Tools->Schematic Viewer->Technology->Start with Explorer Wizard. 
Use filter to quickly find target register. In my case it is named 
"led/cnt_0" (fpga_net.png)

If I'm happy with location of SLICE_X49Y107, I can use the following 
constraint in my UCF file to enforce placement of register "led/cnt_0" 
into this slice:

INST "led/cnt_0" LOC = "SLICE_X49Y107" ;

After this the same LOC constraint should be created for BUFG that is 
clocking this register. If you only lock target slice, ISE may place 
clock buffer in different parts of the chip, this will lead to different 
clock path delays.

If your design passes Translate step without errors, then your LOC 
constraint was successfully applied. If you specify non-existent 
register of invalid target location, your project will not compile, 
because Translate will stop with an error.

One more thing to consider is that enforcing placement may not be enough 
to always get consistent results. In Spartan-6 every slice has 8 
registers. LOC constraint can't control placement within a slice, so 
your target register can end up in different parts of a slice. I don't 
know whether it matters or not, because I don't know how slices are laid 
out in silicon. Another thing to keep in mind is that if your design is 
large, ISE can decide to reuse free registers in your target slice for 
something else. You may want to instantiate slices directly to prevent 
ISE from stuffing unwanted logic in it.

--
With best regards,
Pavel Shatov
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