[Cryptech Core] FPGA Power Estimation

[Павел Шатов]

On 01.06.2015 15:25, Joachim Strömbergson wrote:
> -----BEGIN PGP SIGNED MESSAGE-----
> Hash: SHA256
>
> Aloha!
>
> More FPGA related questions.
>
> I've tried to do some early power estimation for the FPGA on the Alpha
> Board.
>
> I've assembled a design that includes everything from core_selector and
> downwards. That is, the EIM interface is not included. But TRNG, modexp,
> aes, sha256 is. The reason for starting at core_selector is to not have
> to fix the clocking at this stage, instead simply mapping the
> sys-interface to pins on the FPGA. The EIM interface (or FMC when EIM is
> updated) should not make any big difference wrt power consumption (even
> though the PLLs/DCMs and the clock trees consumes power.)
>
> Mapping all ports to 3.3V fast I/Os, setting clock frequency to 66 MHz
> and building for Artix-7 200T and implementing the design. Then using
> the Xilinx Power Analyzer (XPA) tool in ISE.  One can play with the
> toggle rates (and I increased I/O rate from default to 100 (out of
> 200)), increased capacitive load and I still end up with something like
> 0.7W.
>
> Not very much, but the 200T is quite empty. The problem is that we want
> to aim for having more stuff in the FPGA. And having the cores work in
> parallel.
>
> Have you any experience in modelling power with XPA Pavel? And how
> should we model the power consumption to get a good estimate that
> includes future cores? Without instantiating lots if extra cores and
> adding simulation runs to get toggle rates closer to reality? Do we need
> to add the second clock during estimation?
>
>
> The XPA tools seems to be doing basically the same things as the XPE
> spread sheet. I have problems getting the spead sheet to work. The
> buttons for loading/importing mrp files etc are all dead. This on latest
> Excel.
>

Well, I personally have never had any positive experience with that 
Excel spreadsheet either. It's difficult to predict power consumption 
not only because it depends on device utilization, but because it 
depends on internal activity of cores. Suppose, that we have say 10 
cores that make up 90% of FPGA. If only one core gets activated at a 
time, we will have lower current consumption. If all the cores are 
crunching in parallel, we will have much higher current consumption.

Four voltage rails are required for Artix-7: VCCINT (core logic), 
VCCBRAM (block memory), VCCUAX (JTAG, configuration logic, etc), VCCO 
(I/O logic). VCCINT and VCCBRAM can be connected to the same regulator.

I think, that more or less reasonable starting point is AC701 
development board:

VCCINT:  1.0V @ 10A
VCCBRAM: 1.0V @ 3A
VCCAUX:  1.8V @ 6A

Speaking of I/O voltage, I think, that we can power all the I/O banks 
from 3.3V

--
With best regards,
Pavel Shatov