[Cryptech Core] FPGA Power Estimation

[Joachim Strömbergson]

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Aloha!

More FPGA related questions.

I've tried to do some early power estimation for the FPGA on the Alpha
Board.

I've assembled a design that includes everything from core_selector and
downwards. That is, the EIM interface is not included. But TRNG, modexp,
aes, sha256 is. The reason for starting at core_selector is to not have
to fix the clocking at this stage, instead simply mapping the
sys-interface to pins on the FPGA. The EIM interface (or FMC when EIM is
updated) should not make any big difference wrt power consumption (even
though the PLLs/DCMs and the clock trees consumes power.)

Mapping all ports to 3.3V fast I/Os, setting clock frequency to 66 MHz
and building for Artix-7 200T and implementing the design. Then using
the Xilinx Power Analyzer (XPA) tool in ISE.  One can play with the
toggle rates (and I increased I/O rate from default to 100 (out of
200)), increased capacitive load and I still end up with something like
0.7W.

Not very much, but the 200T is quite empty. The problem is that we want
to aim for having more stuff in the FPGA. And having the cores work in
parallel.

Have you any experience in modelling power with XPA Pavel? And how
should we model the power consumption to get a good estimate that
includes future cores? Without instantiating lots if extra cores and
adding simulation runs to get toggle rates closer to reality? Do we need
to add the second clock during estimation?


The XPA tools seems to be doing basically the same things as the XPE
spread sheet. I have problems getting the spead sheet to work. The
buttons for loading/importing mrp files etc are all dead. This on latest
Excel.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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