[Cryptech Core] FPGA Power Estimation

[Joachim Strömbergson]

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Aloha!

Павел Шатов wrote:
> Well, I personally have never had any positive experience with that 
> Excel spreadsheet either. It's difficult to predict power
> consumption not only because it depends on device utilization, but
> because it depends on internal activity of cores. Suppose, that we
> have say 10 cores that make up 90% of FPGA. If only one core gets
> activated at a time, we will have lower current consumption. If all
> the cores are crunching in parallel, we will have much higher current
> consumption.
> 
> Four voltage rails are required for Artix-7: VCCINT (core logic), 
> VCCBRAM (block memory), VCCUAX (JTAG, configuration logic, etc),
> VCCO (I/O logic). VCCINT and VCCBRAM can be connected to the same
> regulator.
> 
> I think, that more or less reasonable starting point is AC701 
> development board:
> 
> VCCINT:  1.0V @ 10A VCCBRAM: 1.0V @ 3A VCCAUX:  1.8V @ 6A
> 
> Speaking of I/O voltage, I think, that we can power all the I/O
> banks from 3.3V

Yes, looking at the reference board for figures (and possibly a design
start) is good. I'll update the values in the XPA tool.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
========================================================================
 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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