[Cryptech Core] Clocking the FPGA using the FMC SRAM clock?

[Pavel Shatov]

On 01.06.2015 10:35, Joachim Strömbergson wrote:
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> Aloha!
>
> Was thinking about the FPGA clocking on the Alpga board.
>
> Pavel, what do you think about using the FMC SRAM source clock as source
> for core clock? Running the cores at 90 MHz might be hard. Half speed
> should be no problem and make for easy synch with the external
> interface, but will be a slower than what we have on the Novena. 3/4
> (using DCM scaling) puts us above Novena and should still allow us to
> use a single source clock.
>
> The one drawback I see is that the FPGA can't be started before the M4
> is up and running... Might not be that good.
>

Well, this is impossible with EIM, because EIM memory clock only gets 
activated by i.MX6Q during read/write transactions, so it can't be used 
as a general-purpose clock for running cores. The same situation may be 
true for STM32F4, I haven't checked, whether it supports continuous 
clocking of memory or not.

Not that I'm opposed to your idea, but I somehow don't see major 
benefits from it. By using DCM to boost core clock, we will still end up 
with two clock domains.

Most FPGA designs that I've seen, have dedicated reference clock 
generator for FPGA. I suggest, that we stick with our current Alpha 
board drawing and keep that 50 MHz oscillator.

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With best regards,
Pavel Shatov