[Cryptech-Commits] [core/util/keywrap] 44/95: Debugged keywrap processing including A update. All AES operations works correctly. Now we just need to stop processing whe we should.
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git at cryptech.is
Wed Mar 25 17:18:43 UTC 2020
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paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.
commit 274862150052b4e62de20a52519a517ef1f9a3ff
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Jul 5 10:24:58 2018 +0200
Debugged keywrap processing including A update. All AES operations works correctly. Now we just need to stop processing whe we should.
---
src/rtl/keywrap_core.v | 12 +++++++-----
src/rtl/keywrap_mem.v | 4 ++--
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index 07a079b..bb7cc09 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -134,6 +134,7 @@ module keywrap_core (
reg update_state;
reg core_we;
+ reg [12 : 0] core_addr;
reg [63 : 0] core_wr_data;
wire [63 : 0] core_rd_data;
@@ -150,7 +151,7 @@ module keywrap_core (
.api_rd_data(api_rd_data),
.core_we(core_we),
- .core_addr(block_ctr_reg),
+ .core_addr(core_addr),
.core_wr_data(core_wr_data),
.core_rd_data(core_rd_data)
);
@@ -230,8 +231,9 @@ module keywrap_core (
begin : keywrap_dp
reg [63 : 0] xor_val;
- a_new = 64'h0;
- a_we = 1'h0;
+ a_new = 64'h0;
+ a_we = 1'h0;
+ core_addr = block_ctr_reg - 1'h1;
core_we = 1'h0;
aes_block = {a_reg, core_rd_data};
@@ -258,12 +260,12 @@ module keywrap_core (
//----------------------------------------------------------------
always @*
begin : block_ctr
- block_ctr_new = 13'h0;
+ block_ctr_new = 13'h1;
block_ctr_we = 1'h0;
if (block_ctr_rst)
begin
- block_ctr_new = 13'h0;
+ block_ctr_new = 13'h1;
block_ctr_we = 1'h1;
end
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index dc08bab..6a70ebe 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -138,10 +138,10 @@ module keywrap_mem (
if (core_we)
begin
- mem0_data = core_wr_data[31 : 0];
+ mem0_data = core_wr_data[63 : 32];
mem0_addr = core_addr;
mem0_we = 1'h1;
- mem1_data = core_wr_data[63 : 32];
+ mem1_data = core_wr_data[31 : 0];
mem1_addr = core_addr;
mem1_we = 1'h1;
end
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