[Cryptech-Commits] [core/util/keywrap] 43/95: Fixed memory word order. Fixed a number of bugs. First block encrypted correctly. A state is wrong and memory is read too far.
git at cryptech.is
git at cryptech.is
Wed Mar 25 17:18:42 UTC 2020
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paul at psgd.org pushed a commit to branch master
in repository core/util/keywrap.
commit 6b15816bff4c0c3ab22bf6d8185da48a263f7727
Author: Joachim Strömbergson <joachim at secworks.se>
AuthorDate: Thu Jul 5 09:58:39 2018 +0200
Fixed memory word order. Fixed a number of bugs. First block encrypted correctly. A state is wrong and memory is read too far.
---
src/rtl/keywrap.v | 4 ++--
src/rtl/keywrap_core.v | 18 ++++++------------
src/rtl/keywrap_mem.v | 2 +-
src/tb/tb_keywrap.v | 22 +++++++++++++++-------
4 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/src/rtl/keywrap.v b/src/rtl/keywrap.v
index 3117f61..69295ed 100644
--- a/src/rtl/keywrap.v
+++ b/src/rtl/keywrap.v
@@ -287,7 +287,7 @@ module keywrap(
if ((address >= ADDR_KEY0) && (address <= ADDR_KEY7))
key_we = 1'h1;
- if (address <= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
+ if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
core_api_we = 1'h1;
end // if (we)
@@ -320,7 +320,7 @@ module keywrap(
if (address == ADDR_A1)
tmp_read_data = core_a_result[31 : 0];
- if (address <= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
+ if (address >= ADDR_R_DATA0 && address <= ADDR_R_DATA127)
tmp_read_data = core_api_rd_data;
end
end
diff --git a/src/rtl/keywrap_core.v b/src/rtl/keywrap_core.v
index e7b7749..07a079b 100644
--- a/src/rtl/keywrap_core.v
+++ b/src/rtl/keywrap_core.v
@@ -127,6 +127,7 @@ module keywrap_core (
reg aes_init;
reg aes_next;
wire aes_ready;
+ wire aes_valid;
reg [127 : 0] aes_block;
wire [127 : 0] aes_result;
@@ -170,7 +171,7 @@ module keywrap_core (
.ready(aes_ready),
.result(aes_result),
- .result_valid()
+ .result_valid(aes_valid)
);
@@ -351,7 +352,10 @@ module keywrap_core (
ready_we = 1'h1;
valid_new = 1'h0;
valid_we = 1'h1;
- keywrap_core_ctrl_new = CTRL_NEXT_START;
+ init_a = 1'h1;
+ block_ctr_rst = 1'h1;
+ iteration_ctr_rst = 1'h1;
+ keywrap_core_ctrl_new = CTRL_NEXT_LOOP;
keywrap_core_ctrl_we = 1'h1;
end
end
@@ -376,16 +380,6 @@ module keywrap_core (
end
- CTRL_NEXT_START:
- begin
- init_a = 1'h1;
- block_ctr_rst = 1'h1;
- iteration_ctr_rst = 1'h1;
- keywrap_core_ctrl_new = CTRL_NEXT_LOOP;
- keywrap_core_ctrl_we = 1'h1;
- end
-
-
CTRL_NEXT_LOOP:
begin
aes_next = 1'h1;
diff --git a/src/rtl/keywrap_mem.v b/src/rtl/keywrap_mem.v
index d31c76c..dc08bab 100644
--- a/src/rtl/keywrap_mem.v
+++ b/src/rtl/keywrap_mem.v
@@ -81,7 +81,7 @@ module keywrap_mem (
// Assignments for ports.
//----------------------------------------------------------------
assign api_rd_data = muxed_api_rd_data;
- assign core_rd_data = {core_rd_data1, core_rd_data0};
+ assign core_rd_data = {core_rd_data0, core_rd_data1};
//----------------------------------------------------------------
diff --git a/src/tb/tb_keywrap.v b/src/tb/tb_keywrap.v
index 6b553ab..2cabca3 100644
--- a/src/tb/tb_keywrap.v
+++ b/src/tb/tb_keywrap.v
@@ -223,7 +223,7 @@ module tb_keywrap();
task dump_mem(integer n);
begin : dump_mem
integer i;
- for (i = 0 ; i < n ; i = i + 2)
+ for (i = 0 ; i < n ; i = i + 1)
$display("mem0[0x%06x] = 0x%08x mem1[0x%06x] = 0x%08x",
i, dut.core.mem.mem0[i], i, dut.core.mem.mem1[i]);
$display("");
@@ -247,7 +247,7 @@ module tb_keywrap();
$display("top level state:");
$display("init_reg = 0x%x next_reg = 0x%x", dut.init_reg, dut.next_reg);
$display("endec_reg = 0x%x keylen_reg = 0x%x", dut.encdec_reg, dut.keylen_reg);
- $display("rlen_reg = 0x%06x", dut.rlen_reg);
+ $display("rlen_reg = 0x%06x r_bank_reg = 0x%06x", dut.rlen_reg, dut.r_bank_reg);
$display("a0_reg = 0x%08x a1_reg = 0x%08x", dut.a0_reg, dut.a1_reg);
$display("");
end
@@ -257,22 +257,33 @@ module tb_keywrap();
$display("core level state:");
$display("init = 0x%0x next = 0x%0x ready = 0x%0x valid = 0x%0x",
dut.core.init, dut.core.next, dut.core.ready, dut.core.valid);
+ $display("api_we = 0x%0x api_addr = 0x%0x api_wr_data = 0x%0x api_rd_data = 0x%0x",
+ dut.core.api_we, dut.core.api_addr, dut.core.api_wr_data, dut.core.api_rd_data);
$display("rlen = 0x%0x", dut.core.rlen);
$display("key = 0x%0x", dut.core.key);
$display("a_init = 0x%0x a_result = 0x%0x", dut.core.a_init, dut.core.a_result);
$display("");
+
$display("update_state = 0x%0x", dut.core.update_state);
$display("a_reg = 0x%0x a_new = 0x%0x a_we = 0x%0x",
dut.core.a_reg, dut.core.a_new, dut.core.a_we);
- $display("aes_block = 0x%0x aes_result = 0x%0x",
- dut.core.aes_block, dut.core.aes_result);
$display("core_we = 0x%0x core_addr = 0x%0x",
dut.core.core_we, dut.core.block_ctr_reg);
$display("core_rd_data = 0x%0x core_wr_data = 0x%0x ",
dut.core.core_rd_data, dut.core.core_wr_data);
$display("");
+
+ $display("aes_ready = 0x%0x aes_valid = 0x%0x",
+ dut.core.aes_ready, dut.core.aes_valid);
+ $display("aes_init = 0x%0x aes_next = 0x%0x",
+ dut.core.aes_init, dut.core.aes_next);
+ $display("aes_block = 0x%0x aes_result = 0x%0x",
+ dut.core.aes_block, dut.core.aes_result);
+ $display("");
+
+
$display("block_ctr_reg = 0x%0x iteration_ctr_reg = 0x%0x",
dut.core.block_ctr_reg, dut.core.iteration_ctr_reg);
$display("keywrap_core_ctrl_reg = 0x%0x", dut.core.keywrap_core_ctrl_reg);
@@ -363,9 +374,6 @@ module tb_keywrap();
write_word(ADDR_KEY3, 32'ha8d77e3d);
write_word(ADDR_CONFIG, 32'h00000001);
- $display("* State after key has been set:");
- dump_dut_state();
-
// Initialize the AES engine (to expand the key).
// Wait for init to complete.
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