[Open Crypto Project] #42: FPGA field upgrade

[Open Crypto Project]

#42: FPGA field upgrade
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 Reporter:  pselkirk  |       Owner:
     Type:  task      |      Status:  new
 Priority:  major     |   Milestone:  Alpha board DNSSEC signer
Component:  HAL       |     Version:
 Keywords:            |  Blocked By:
 Blocking:            |
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 For initial development, the FPGA can be configured through a Xilinx JTAG
 cable.

 In the longer term, we need a software reconfiguration mechanism. For
 purposes of timing and safety, this will be a two-stage transfer: 1)
 Transfer the bitstream from the PC to ARM working memory over USB, and
 validate the checksum; 2) transfer from ARM working memory to FPGA config
 memory (N25Q128A13ES flash) over SPI.

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Ticket URL: <https://trac.cryptech.is/ticket/42>
Open Crypto Project <https://wiki.cryptech.is/>