[Cryptech Tech] Selection of Lattice FPGA as key memory for the Alpha board

[Peter Stuge]

Hi Pavel,

Pavel Shatov wrote:
> doing the actual edits to the rev.03 hardware design to make it rev.04.

What's the plan for this? In particular, are you editing in KiCad or Altium?


Also more generally; I've noticed another signal that I would like to
have added to the UART daughterboard headers; DTR.


> 1. Configuration. Basically we have three options:
> 1.1 NVCM. This is an internal one-time programmable non-volatile
> 1.2 Master SPI. This is equivalent to the scheme we have for the main Artix-7
> 1.3 Slave SPI. ... not try to use NVMC and will just passively wait for STM32

I favor Slave SPI for development, while ensuring that NVCM remains
an option for later. I think this is possible by STM32 firmware
monitoring CDONE for a while, and only attempting to configure if
CDONE is still not asserted after a suitable timeout.


> 2. Clocking
> 
> I think we need to first clarify, whether the MKM needs any clock 
> source. I mean, if the device behaves like an SPI slave, in theory it 
> only needs SCLK, but some other clock source may be needed, for say 
> periodically polling some sensor or measuring timeouts, etc.

I want a clock, so that the MKM can periodically flip the key bits in RAM.


> LP/HX/LM devices don't have internal oscillators, so they all need
> an external clock crystal.

Would it be possible to create a ring oscillator in logic in those devices?


> Note, that there's an additional series of iCE40 UltraPlus devices,
> that do have at once two internal oscillators

A UltraPlus, Ultra or UltraLite device seems like a strong candidate.

Maybe it makes sense to have both an FPGA-internal clock source and an
external one? They can monitor each other.

Ultra and UltraLite have the same two oscillators as UltraPlus, fewer LUTs
and the same packaging. I suppose Ultra and UltraLite are UltraPlus devices
that failed production testing to some degree. To me that's an argument in
favor of an UltraPlus device, but on the other hand I think a part with
fewer LUTs also has some benefits - it further reduces the possibility
of the MKM doing something unwanted.


> 3. I/O Pins
> 6 pins

I think another few pins to STM32 and/or FPGA would be good. Especially
if we do move tamper detection into the FPGA (I am in favor of this) then
it's nice for the MKM to be able to let everyone know that something has
happened with an interrupt signal.


> All in all, I tend to think, that the UP5K (UltraPlus 5K) device would 
> be the optiomal choice. It comes in either 30-pin WLCSP package with 21 
> user I/O pins or 48-pin QFN with 39 user I/Os. Currently the QFN looks 
> more friendly, but I haven't yet looked at Lattice recommendations 
> regarding their teeny weeny WLCSP and BGA packages.

iCE40UP5K-SG48I is the largest in terms of LUTs, and while 5k LUTs seems
quite excessive for the simple MKM task that we have in mind I can understand
the desire to give ourselves as much room as possible for experiments.


Thanks

//Peter