[Cryptech Tech] Selection of Lattice FPGA as key memory for the Alpha board

[Pavel Shatov]

Hi,

okay, yes, this thread is more than a month old, but I've finally got my 
hands on doing the actual edits to the rev.03 hardware design to make it 
rev.04.

The crucial part at the moment is to pick the specific partnumber out of 
the Lattice iCE40 family to replace the master key memory. Joachim has 
already outlined the factors we should consider, and my thoughts are below.


1. Configuration. Basically we have three options:

1.1 NVCM. This is an internal one-time programmable non-volatile 
configuration memory. I suspect we won't use it right away, since at 
least some amount of debugging and re-programming will be necessary. As 
far as I understand, the easiest way to program NVCM is to just buy a 
Lattice cable. They also say NVCM can be programmed from an external 
processor, but tell to contact their support for details.

Note, that there's an interesting white paper claiming that it's 
impossible to extract the programmed data from NCVM even using electron 
microscopy:
https://www.latticesemi.com/-/media/LatticeSemi/Documents/WhitePapers/NZ/SecurityAspectOfLatticeSemiconductor-English-090313.ashx?document_id=50737

1.2 Master SPI. This is equivalent to the scheme we have for the main 
Artix-7 FPGA. Some small commodity PROM (maybe the same family we use 
for the Artix-7 bitstream, but smaller density) can be attached to 
iCE40. STM32 will program this PROM, Lattice device will then read the 
bitstream from this PROM and configure itself. As far as I understand 
from the corresponding technical note on iCE40 programming and 
configuration, NVCM and Master SPI are mutually exclusive, i.e. iCE40 
will always try to configure from NVCM first, if NCVM is unprogrammed, 
it will fallback to Master SPI.

1.3 Slave SPI. This way every time the board is powered up, iCE40 will 
not try to use NVMC and will just passively wait for STM32 to directly 
send it the configuration bitstream. This variant doesn't involve an 
extra PROM chop, but unlike the previous master variant, it requires 
some actions on the STM32 side to get the master key memory operational. 
We also need to store the bitstream somewhere, one option is to use the 
extra space at the end of the PROM chip where the main bitstream is 
stored, for example.


2. Clocking

I think we need to first clarify, whether the MKM needs any clock 
source. I mean, if the device behaves like an SPI slave, in theory it 
only needs SCLK, but some other clock source may be needed, for say 
periodically polling some sensor or measuring timeouts, etc. Joachim 
said he wanted a device with a PLL to not depend on an external clock, I 
didn't quite understand this. A PLL can only generate an output 
frequency out of some input reference frequency, it can't be used as an 
oscillator.

I took a closer look at the iCE40 family and it turns out LP/HX/LM 
devices don't have internal oscillators, so they all need an external 
clock crystal. Note, that there's an additional series of iCE40 
UltraPlus devices, that do have at once two internal oscillators: "slow" 
10 kHz for housekeeping needs and "fast" 48 MHz, the latter one can be 
divided to 24, 12 or 6 MHz as needed. The good news is UltraPlus *is* 
supported by IceStorm. It also has slightly lower power consumption than 
the LP1K device (75 vs 100 uA static current).


3. I/O Pins

iCE40 devices have several package options, and consequently different 
numbers of I/O pins. As far as I understand, we need a minimum of 6 pins 
between the main FPGA and Lattice device. One extra clock pin will be 
required, if we don't go for the UltraPlus family with built-in 
oscillators. I also remember certain discussions about removing the AVR 
tamper detection processor and assigning the job to the Lattice device. 
Currently we have 21 user I/O pins in the AVR: 4x LEDs, 1x panic button, 
4x GPIO for STM32, 4x GPIO for Artix-7, 8x header for external sensors.


All in all, I tend to think, that the UP5K (UltraPlus 5K) device would 
be the optiomal choice. It comes in either 30-pin WLCSP package with 21 
user I/O pins or 48-pin QFN with 39 user I/Os. Currently the QFN looks 
more friendly, but I haven't yet looked at Lattice recommendations 
regarding their teeny weeny WLCSP and BGA packages.


26.03.2020 13:37, Joachim Strömbergson пишет:

> Aloha!
> 
> Continuing regarding programming. Writing to the NVCM seems to be done
> in three ways:
> 
> 1. Using a Lattice Diamond Programmer attached to the hard SPI interface
> in the device. At least some pads or a header on the board would be
> required. And getting a Diamong Programmer.
> 
> 2. From a CPU host. In Alpha board context this would either be an
> external host (connected via a header), the STM32, or via the big FPGA.
> Unfortunately how this is to be done is not specified. "For more
> information contact your local Lattice sales office."
> 
> 3. Have the chips be programmed by Lattice prior to delivery. This would
> probably require a minimum volume greater than what we plan for. More
> importantly, I don't see us wanting a third party programming the master
> key handling and tamper response functionality for us. That would be yet
> a new black box.
> 
> So, either 1 or 2. There is also the ability to load the config directly
> from an external source (including a host), that is not writing to the
> NVCM. This is how the iCESTICK works. At least for testing. An incorrect
> write to the NVCM would have quite severe impact.
> 
> Regards,
> JoachimS
> 
> On 2020-03-26 11:19, Joachim Strömbergson wrote:
>> Aloha!
>>
>> Replying to myself here. Reading up on device programming I found an issue:
>>
>> [iCE40 Programming and
>> Configuration](http://www.latticesemi.com/view_document?document_id=46502)
>>
>> It turns out that the LM versions of iCE40 lacks the in-package
>> non-volatile configuration memory (NVCM). We want to have this memory.
>> This removes the LM-device below from the list of candidates. The
>> LP-versions includes the NVCM.
>>
>> Regards,
>> JoachimS
>>
>>
>> On 2020-03-24 16:34, Joachim Strömbergson wrote:
>>> Aloha!
>>>
>>> (Lets do this on @tech. Hopefully somebody else want to chime in with
>>> suggestions and ideas.)
>>>
>>> Pavel, I’ve looked at possible FPGA devices to be integrated onto the
>>> new Cryptech board to be used as FPGA based master key memory
>>> (fpga_mkm). Here are my reasoning for the devices I’ve selected.
>>>
>>> We want to use a device supported by the Project IceStorm toolchain:
>>> [Project IceStorm"](http://www.clifford.at/icestorm/). The toolchain
>>> supports a number of devices in the iCE40 LP/HX/LM series:
>>> https://www.latticesemi.com/Products/FPGAandCPLD/iCE40
>>>
>>> We are currently using the iCEstick evaluation board for the
>>> development. The iCEstick is supported by the toolchain. [iCEstick
>>> Evaluation Kit - Lattice
>>> Semiconductor](http://www.latticesemi.com/en/Products/DevelopmentBoardsAndKits/iCEstick).
>>>
>>> The dev board sports a iCE40HX1K device. Judging by resource numbers we
>>> are currently using 15% of the Programmable Logic Blocks. This means
>>> that we could use a smaller device. But the 1K-devices contain an PLL
>>> that can be used as clock source (meaning no external clock). I would
>>> therefore suggest that we choose one of the 1K-devices.
>>>
>>> We also need very few I/Os. We currently use nine I/Os, and one is for
>>> clock and two are just for debugging (red and green LEDs)
>>>
>>> Based on this, and looking at availability, I have the following LP1L
>>> devices on my list:
>>>
>>> * [ICE40LP1K-SWG16TR Lattice Semiconductor Corporation | Integrated
>>> Circuits (ICs) |
>>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LP1K-SWG16TR/ICE40LP1K-SWG16TR-ND/4572398).
>>>
>>> * [ICE40LP1K-CM36 Lattice Semiconductor Corporation | Integrated
>>> Circuits (ICs) |
>>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LP1K-CM36/220-1564-ND/3083574)
>>>
>>> The 16-ball WLCSP has 0.35 mm spacing and the 36-ball ucBGA has 0.40 mm
>>> spacing.
>>>
>>>  From LM1K I would suggest:
>>> * [ICE40LM1K-SWG25TR Lattice Semiconductor Corporation | Integrated
>>> Circuits (ICs) |
>>> DigiKey](https://www.digikey.com/product-detail/en/lattice-semiconductor-corporation/ICE40LM1K-SWG25TR/ICE40LM1K-SWG25TR-ND/4572404)
>>>
>>> The 25-ball WLCSP has 0.35 mm spacing.
>>>
>>> All devices seems to be in active production and accessible in single
>>> quantities for around 3 USD. Do you think any of these would work?
>>> Anyone that you prefer?
>>>
>>> I haven’t looked at how we are going to program the devices on the
>>> board. The devices contain a Flash based config memory that can be
>>> programmed and then locked. This is a feature we want to use.
>>>
>>>
>>> _______________________________________________
>>> Tech mailing list
>>> Tech at cryptech.is
>>> https://lists.cryptech.is/listinfo/tech
>>>
>>
>>
>>
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-- 
With best regards,
Pavel Shatov