[Cryptech Tech] Comments on Alpha board schematics

[Fredrik Thulin]

On Wednesday, January 27, 2016 08:15:57 PM Joachim Strömbergson wrote:
> Aloha!
> 
> Joachim Strömbergson wrote:
> > Sure I'm happy to talk about it. I don't think it is a matter of
> > ambition though. It is a matter of how the TRNG works and will be
> > working in v2 and how the systen inside of the FPGA will evolve.
> 
> I had a good, long walk home today and got to spend time thinking 
about
> the entropy source power control. And I was wrong. At least partially.
> It should be solvable fairly easy.
> 
> It should be quite feasible to tie power up signalling to the 
(inverse)
> fifo full signal in the mixer output fifo. This fifo can store n seeds
> needed by the CSPRNG to do n/2 reseeds. If the fifo is full we know 
that
> unless reseeding happens too often, we should have enough time to 
power
> up the entropy source, wait for it to warm up, assess its noise 
quality
> and generate new seeds.

Clever thinking, that would be the last 1% of complexity ;).

Let me see if I understand you right - you are saying that after HSM 
boot up, we seed the PRNG *and* store enough entropy for the next 
reseed? The next reseed is then non-blocking because the entropy is 
already available.

Right after the next reseed has happened we start the entropy sources 
again, do all the tests, and again buffer enough entropy for the next 
reseed so that it too will be non-blocking?

/Fredrik
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