[Cryptech Tech] Comments on Alpha board schematics

[Joachim Strömbergson]

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Aloha!

Joachim Strömbergson wrote:
> Sure I'm happy to talk about it. I don't think it is a matter of 
> ambition though. It is a matter of how the TRNG works and will be 
> working in v2 and how the systen inside of the FPGA will evolve.

I had a good, long walk home today and got to spend time thinking about
the entropy source power control. And I was wrong. At least partially.
It should be solvable fairly easy.

It should be quite feasible to tie power up signalling to the (inverse)
fifo full signal in the mixer output fifo. This fifo can store n seeds
needed by the CSPRNG to do n/2 reseeds. If the fifo is full we know that
unless reseeding happens too often, we should have enough time to power
up the entropy source, wait for it to warm up, assess its noise quality
and generate new seeds.

Parameters affecting the behaviour are:
- - Number of positions in the fifo.
- - The reseed frequency

We might also want to have a timeout counter to allow us to keep the
entropy sourced powered up for a given number of cycles after the fifo
has been filled. This allows for a fast reseed.

I can see one potential problem. When we exit the test mode we don't
want any residual test data state to be present. We therefore clear all
fifos and state in entropy sources, mixer and csprng. A simple solution
is to always have the entropy source powered up when in test mode. It
seems natural.

- -- 
Med vänlig hälsning, Yours

Joachim Strömbergson - Alltid i harmonisk svängning.
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 Joachim Strömbergson          Secworks AB          joachim at secworks.se
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