[Cryptech Tech] Where can be found the lastest version of the CSPRNG designed for the novena ?

[★ STMAN ★]

Thank you very much !

Glad to see you have perfectly documented everything and implemented it on several FPGA, at least, Xilinx and Altera ! I have been following some of the technical discussions you had in the mailing list for more than a year, and I really appreciated the way this project was conducted.

Let me download everything, read the docs carefully, and I will be back to you very soon !

Kind regards,

Frederic.



Le 12 janv. 2016 à 10:03, Joachim Strömbergson <joachim at secworks.se> a écrit :

> Signé partie PGP
> Aloha!
> 
> Welcome to the Cryptech project!
> 
> ★ STMAN ★ wrote:
> > Hi everybody !
> >
> > I need to get the lastest version of the CSPRNG you have developped
> > these two last years for the Novena, in order to integrate it into
> > another Free and Open project I am working on
> ...
> >
> > I order to finalize this development, it now time for me to
> > integrate a trustable PRNG into the design of the processor itself,
> > in order to secure a few things. Could the lead developper in charge
> > of the CSPRNG here could get in touch with me in order to feed me
> > with the latest source code (VHDL) AND documentation AND schematics,
> > plus the licensing conditions (GPL I guess ?) ?
> 
> I'm the lead developer of the TRNG and will gladly answer any questions
> you have. Let me give a short description first and then answer your
> current question.
> 
> The Cryptech TRNG is a hybrid RNG with two separate entropy sources that
> feeds a digital chain implemented in the FPGA. The main entropy source
> is based on avalanche noise and is designed by Fredrik Thulin and
> Benedict Stockebrand. Schematics for this entropy source is available here:
> 
> http://wiki.cryptech.is/browser/doc/design/Novena-entropy-board
> 
> The second entropy source is implemented in the FPGA and is based on
> jitter between multiple free running digital oscillators. The source is
> designed by Bernd Paysan and me. This entropy source must be qualified
> for the given FPGA family you want to use and the layout should
> preferably be locked down to ensure similar behavior between separate
> builds. The source has been tested in both Altera and Xilinx devices.
> The source for it is available here:
> 
> http://wiki.cryptech.is/browser/core/rng/rosc_entropy
> 
> The PRNG part of the generator comprises of an entropy source mixer
> implemented using SHA-512 and a CSPRNG implemented using the stream
> cipher ChaCha. There are also some fifos etc. All cores needed to
> implement the TRNG are available here:
> 
> http://wiki.cryptech.is/wiki/GitRepositories
> 
> The top level for the TRNG is here:
> http://wiki.cryptech.is/browser/core/rng/trng
> 
> As you can see from the source code, we use Verilog (2001-ish) as RTL
> language. All our code is licensed under a 3-clause BSD license.
> Schematics, documentation are licensed under Creative Commons.
> 
> --
> Med vänlig hälsning, Yours
> 
> Joachim Strömbergson - Alltid i harmonisk svängning.
> ========================================================================
> Joachim Strömbergson          Secworks AB          joachim at secworks.se
> ========================================================================
> 

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