[Cryptech Tech] Alpha layout done (not a joke)

[Jacob]

On 4/4/2016 12:05 PM, Pavel Shatov wrote:
> On 02.04.2016 9:43, Jacob wrote:
>>
>> Additional comments:

>> 2. I guess that supposedly there are 4 mechanical mounting holes at the
>> 4 corners of the board. However, only the bottom two are proper holes.
>> The top 2 are not.
>
> Well, that's how Intel's 3D model got imported into Altium. The two top
> holes are actually not round, but oval and they are part of board
> outline. The bottom two holes are just regular unplated drills. Do you
> suggest removing the two top holes from board outline and moving them to
> a new unplated milling contour?

It is recommended to make holes like that (either round or oval) as a 
unplated drill entity and not board cut-out, so the fabricator will 
clearly see this on the drill table with the proper dimensions, without 
the need to measure it off the gerber file.
But, if you call those oval board cut-out on the drill drawing saying 
"OVAL CUTOUT PER GERBER CONTOUR (X2)" it will also do, but is a bit less 
desirable.

>
>> 3. Most of the large vias that come out of the decoupling capacitors are
>> too close to comfort to the capacitor pads. In many cases the clearance
>> between the soldermask of the decap pad and the via hole is 4 mil
>> (0.1mm) - a border line case that with the slightest manufacturing
>> deviation will render the gap w/o solder mask (not a good thing).
>
> Jacob, I'm sorry, could you please explain this a a bit? Large vias (I'm
> assume you're talking about 0.5/1.0mm hole/pad ones) will be filled
> according to IPC 4761 Type VII ("via-in-pad").
>

Yes, I am talking about the 0.5/1mm vias. I have noticed that you plate 
those too, but in my mind I just rejected that operation when I wrote my 
comment... why would you want to fill and plate those vias? the only 
vias that require this *expensive* operation are the via-in-pad on the 
FPGA pins.
For all other vias, there is no need to fill&plate - you may just have 
them covered with the solder mask as the rest of the circuit.
And if they are covered with just a solder mask, one should make sure 
that the via hole is, at the abs. min, more than 0.1mm away from any 
nearby solder-masked pad to avoid the possibility of solder being sucked 
into the via hole (especially that 0.5mm dia hole does not always get 
properly filled with soldermask). A 0.15mm or more between via hole and 
nearby soldermask opening is recommended.

See attached pic as an example for current situation, where the distance 
is too small - 0.08mm.
-----------------------------

Some comments about the silk:

1. I suggest to increase the font size of the version/copyright/URL and 
move it to an area clear of vias. 1.5/2mm text height would be good.

2. The Cryptech logo - to move a bit down so the last character will not 
be drilled out by the vias

the issues of text on via assume that you do not fill & plate the vias...)

3. The text by the power input, saying 18-20V, is too small and uses too 
thick a text line - it will come out illegible.

4. The "+" marking by the Tantalum capacitor is too small. I suggest to 
make it 1.5/2mm high.

Please note that abs. min. legible text height at a good fabricator 
house is 0.9mm. 1mm height is reasonably readable but very small, and 
normally being used for Ref. Des. nomenclature at tight places.

Jacob



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